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用于异构集成3D-CFET逻辑电路的晶圆级高迁移率二维碲薄膜晶体管

Wafer-Scale High Mobility 2D Tellurium Thin-Film Transistor for Heterogeneous Integrated 3D-CFET Logic Circuits.

作者信息

Tang Yalun, Song Yilong, Zeng Longhui, Lo Yu-Hwa, Nomura Kenji

机构信息

Department of Electrical and Computer Engineering, University of California San Diego, 9500 Gilman Dr., La Jolla, California, 92093, United States.

Materials Science and Engineering program, Jacobs School of Engineering, University of California San Diego, La Jolla, California, 92093, United States.

出版信息

Small. 2025 Sep;21(35):e2504908. doi: 10.1002/smll.202504908. Epub 2025 Jul 9.

Abstract

Back-end-of-line (BEOL)-compatible complementary field-effect transistor (CFET), which vertically integrates p-channel and n-channel thin-film transistors (TFT) in a 3D architecture on Si-CMOS, is critical for next-generation electronics, enabling higher functionality and improved energy efficiency. However, the absence of a high-performance BEOL-compatible p-channel TFT, the counterpart of n-channel oxide-TFT, continues to pose a significant challenge for the development of wafer-scale CFET technology. Tellurium (Te) has recently emerged as a promising candidate for p-channel TFT, but its device performance is not yet satisfactory. Here, in-plane crystal-oriented 2D Te channel thin-film is successfully grown to improve its carrier transport and successfully demonstrated high mobility p-channel Te-TFT with high saturation mobility (≈31 cm V s). The maximum process temperature is as low as 150 °C, enabling the fabrication of 3D-vertical CFET device with heterogeneous integration with oxide-TFTs on a 2-inch wafer. The hybrid CFET, composed of 2D p-Te and n-a-IGZO TFTs, exhibits an excellent inverter characteristic with a high voltage gain of 162 at V = 4 V. This study highlights the potential of low-temperature processed p-channel Te-TFTs for BEOL heterogeneous-compatible integration with oxide-TFT technology, providing enhanced functionality and high energy-efficiency for next-generation electronics.

摘要

后端兼容互补场效应晶体管(CFET)在硅互补金属氧化物半导体(Si-CMOS)的三维架构中垂直集成了p沟道和n沟道薄膜晶体管(TFT),这对下一代电子产品至关重要,能够实现更高的功能和更高的能源效率。然而,缺乏与后端兼容的高性能p沟道TFT(n沟道氧化物TFT的对应物),仍然是晶圆级CFET技术发展的重大挑战。碲(Te)最近成为p沟道TFT的一个有前途的候选材料,但其器件性能仍不尽人意。在此,成功生长了面内晶体取向的二维碲沟道薄膜以改善其载流子传输,并成功展示了具有高饱和迁移率(≈31 cm² V⁻¹ s⁻¹)的高迁移率p沟道碲TFT。最高工艺温度低至150°C,能够在2英寸晶圆上制造与氧化物TFT进行异质集成的三维垂直CFET器件。由二维p-Te和n-a-IGZO TFT组成的混合CFET在V = 4 V时表现出优异的反相器特性,电压增益高达162。这项研究突出了低温处理的p沟道碲TFT与氧化物TFT技术进行后端异质兼容集成的潜力,为下一代电子产品提供了增强的功能和高能效。

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