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采用与CMOS兼容的绝缘体上硅代工工艺制造的挥发性和非挥发性纳米机电开关。

Volatile and non-volatile nano-electromechanical switches fabricated in a CMOS-compatible silicon-on-insulator foundry process.

作者信息

Li Yingying, Bleiker Simon J, Worsey Elliott, Dagon Maël, Edinger Pierre, Takabayashi Alain Yuji, Quack Niels, Verheyen Peter, Bogaerts Wim, Gylfason Kristinn B, Pamunuwa Dinesh, Niklaus Frank

机构信息

KTH Royal Institute of Technology, 11428, Stockholm, Sweden.

University of Bristol, BS8 1UB, Bristol, UK.

出版信息

Microsyst Nanoeng. 2025 Jul 11;11(1):140. doi: 10.1038/s41378-025-00964-w.

DOI:10.1038/s41378-025-00964-w
PMID:40645929
原文链接:https://pmc.ncbi.nlm.nih.gov/articles/PMC12254297/
Abstract

Nanoelectromechanical (NEM) switches have the advantages of zero leakage current, abrupt switching characteristics, and harsh environmental capabilities. This makes them a promising component for digital computing circuits when high energy efficiency under extreme environmental conditions is important. However, to make NEM-based logic circuits commercially viable, NEM switches must be manufacturable in existing semiconductor foundry platforms to guarantee reliable switch fabrication and very large-scale integration densities, which remains a big challenge. Here, we demonstrate the use of a commercial silicon-on-insulator (SOI) foundry platform (iSiPP50G by IMEC, Belgium) to implement monolithically integrated silicon (Si) NEM switches. Using this SOI foundry platform featuring sub-200 nm lithography technology, we implemented two different types of NEM switches: (1) a volatile 3-terminal (3-T) NEM switch with a low actuation voltage of 5.6 V and (2) a bi-stable 7-terminal (7-T) NEM switch, featuring either volatile or non-volatile switching behavior, depending on the switch contact design. The experimental results presented here show how an established CMOS-compatible SOI foundry process can be utilized to realize highly integrated Si NEM switches, removing a significant barrier towards scalable manufacturing of high performance and high-density NEM-based programmable logic circuits and non-volatile memories.

摘要

纳米机电(NEM)开关具有零漏电流、突变开关特性和适应恶劣环境的能力。当在极端环境条件下实现高能效很重要时,这些特性使它们成为数字计算电路中一种很有前景的元件。然而,要使基于NEM的逻辑电路具有商业可行性,NEM开关必须能够在现有的半导体制造平台上制造,以确保可靠的开关制造和非常大规模的集成密度,而这仍然是一个巨大的挑战。在此,我们展示了使用商业绝缘体上硅(SOI)制造平台(比利时IMEC公司的iSiPP50G)来实现单片集成的硅(Si)NEM开关。利用这种具有低于200纳米光刻技术的SOI制造平台,我们实现了两种不同类型的NEM开关:(1)一种驱动电压低至5.6伏的易失性三端(3-T)NEM开关;(2)一种双稳态七端(7-T)NEM开关,其开关行为根据开关触点设计可为易失性或非易失性。此处给出的实验结果表明,如何利用成熟的与CMOS兼容的SOI制造工艺来实现高度集成的Si NEM开关,消除了高性能、高密度基于NEM的可编程逻辑电路和非易失性存储器可扩展制造的一个重大障碍。

https://cdn.ncbi.nlm.nih.gov/pmc/blobs/cef8/12254297/446a8ffc38e5/41378_2025_964_Fig5_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/cef8/12254297/2bb2791e9b08/41378_2025_964_Fig1_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/cef8/12254297/c28cd1a611c9/41378_2025_964_Fig2_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/cef8/12254297/e98c963fabe3/41378_2025_964_Fig3_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/cef8/12254297/d17742f83baa/41378_2025_964_Fig4_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/cef8/12254297/446a8ffc38e5/41378_2025_964_Fig5_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/cef8/12254297/2bb2791e9b08/41378_2025_964_Fig1_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/cef8/12254297/c28cd1a611c9/41378_2025_964_Fig2_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/cef8/12254297/e98c963fabe3/41378_2025_964_Fig3_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/cef8/12254297/d17742f83baa/41378_2025_964_Fig4_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/cef8/12254297/446a8ffc38e5/41378_2025_964_Fig5_HTML.jpg

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Microsyst Nanoeng. 2023 Jun 7;9:74. doi: 10.1038/s41378-023-00549-5. eCollection 2023.
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Nat Commun. 2020 Mar 4;11(1):1181. doi: 10.1038/s41467-020-14872-2.
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CMOS MEMS Fabrication Technologies and Devices.互补金属氧化物半导体微机电系统制造技术与器件
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