Fritz Sandra E, Kelley Tommie Wilson, Frisbie C Daniel
Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Avenue SE, Minneapolis, Minnesota 55455, USA.
J Phys Chem B. 2005 Jun 2;109(21):10574-7. doi: 10.1021/jp044318f.
The morphology, structure, and transport properties of pentacene thin film transistors (TFTs) are reported showing the influence of the gate dielectric surface roughness. Upon roughening of the amorphous SiO2 gate dielectric prior to pentacene deposition, dramatic reductions in pentacene grain size and crystallinity were observed. The TFT performance of pentacene films deposited on roughened substrates showed reduced free carrier mobility, larger transport activation energies, and larger trap distribution widths. Spin coating roughened dielectrics with polystyrene produced surfaces with 2 A root-mean-square (rms) roughness. The pentacene films deposited on these coated surfaces had grain sizes, crystallinities, mobilities, and trap distributions that were comparable to the range of values observed for pentacene films deposited on thermally grown SiO2 (roughness also approximately 2 A rms).
报告了并五苯薄膜晶体管（TFT）的形态、结构和传输特性，展示了栅极电介质表面粗糙度的影响。在并五苯沉积之前对非晶态SiO₂栅极电介质进行粗糙化处理后，观察到并五苯晶粒尺寸和结晶度显著减小。沉积在粗糙化衬底上的并五苯薄膜的TFT性能表现出自由载流子迁移率降低、传输活化能增大以及陷阱分布宽度增大。用聚苯乙烯旋涂粗糙化的电介质产生了均方根（rms）粗糙度为2 Å的表面。沉积在这些涂覆表面上的并五苯薄膜的晶粒尺寸、结晶度、迁移率和陷阱分布与沉积在热生长SiO₂上的并五苯薄膜（粗糙度也约为2 Å rms）所观察到的值范围相当。
