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一种每平方厘米图案化有10¹¹比特的160千比特分子电子存储器。

A 160-kilobit molecular electronic memory patterned at 10(11) bits per square centimetre.

作者信息

Green Jonathan E, Choi Jang Wook, Boukai Akram, Bunimovich Yuri, Johnston-Halperin Ezekiel, DeIonno Erica, Luo Yi, Sheriff Bonnie A, Xu Ke, Shin Young Shik, Tseng Hsian-Rong, Stoddart J Fraser, Heath James R

机构信息

Division of Chemistry and Chemical Engineering and the Kavli Nanoscience Institute, Caltech, Pasadena, California 91125, USA.

出版信息

Nature. 2007 Jan 25;445(7126):414-7. doi: 10.1038/nature05462.

Abstract

The primary metric for gauging progress in the various semiconductor integrated circuit technologies is the spacing, or pitch, between the most closely spaced wires within a dynamic random access memory (DRAM) circuit. Modern DRAM circuits have 140 nm pitch wires and a memory cell size of 0.0408 mum(2). Improving integrated circuit technology will require that these dimensions decrease over time. However, at present a large fraction of the patterning and materials requirements that we expect to need for the construction of new integrated circuit technologies in 2013 have 'no known solution'. Promising ingredients for advances in integrated circuit technology are nanowires, molecular electronics and defect-tolerant architectures, as demonstrated by reports of single devices and small circuits. Methods of extending these approaches to large-scale, high-density circuitry are largely undeveloped. Here we describe a 160,000-bit molecular electronic memory circuit, fabricated at a density of 10(11) bits cm(-2) (pitch 33 nm; memory cell size 0.0011 microm2), that is, roughly analogous to the dimensions of a DRAM circuit projected to be available by 2020. A monolayer of bistable, [2]rotaxane molecules served as the data storage elements. Although the circuit has large numbers of defects, those defects could be readily identified through electronic testing and isolated using software coding. The working bits were then configured to form a fully functional random access memory circuit for storing and retrieving information.

摘要

衡量各种半导体集成电路技术进展的主要指标是动态随机存取存储器(DRAM)电路中最紧密间隔的导线之间的间距,即节距。现代DRAM电路的导线节距为140纳米,存储单元尺寸为0.0408平方微米。随着时间的推移,集成电路技术的进步需要这些尺寸减小。然而,目前我们预计2013年构建新集成电路技术所需的大部分光刻和材料要求“尚无已知解决方案”。如单个器件和小型电路的报告所示,纳米线、分子电子学和容错架构是集成电路技术进步的有前景的要素。将这些方法扩展到大规模、高密度电路的方法在很大程度上尚未得到开发。在此,我们描述了一种160,000位的分子电子存储电路,其制造密度为10的11次方位每平方厘米(节距33纳米;存储单元尺寸0.0011平方微米),也就是说,大致类似于预计到2020年可获得的DRAM电路的尺寸。一层双稳态[2]轮烷分子用作数据存储元件。尽管该电路有大量缺陷,但这些缺陷可以通过电子测试轻松识别,并使用软件编码进行隔离。然后将工作位配置成一个功能齐全的随机存取存储电路,用于存储和检索信息。

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