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基于忆阻器的非易失性锁存电路。

A memristor-based nonvolatile latch circuit.

机构信息

Hewlett Packard Labs, Palo Alto, CA, USA.

出版信息

Nanotechnology. 2010 Jun 11;21(23):235203. doi: 10.1088/0957-4484/21/23/235203. Epub 2010 May 17.

DOI:10.1088/0957-4484/21/23/235203
PMID:20472941
Abstract

Memristive devices, which exhibit a dynamical conductance state that depends on the excitation history, can be used as nonvolatile memory elements by storing information as different conductance states. We describe the implementation of a nonvolatile synchronous flip-flop circuit that uses a nanoscale memristive device as the nonvolatile memory element. Controlled testing of the circuit demonstrated successful state storage and restoration, with an error rate of 0.1%, during 1000 power loss events. These results indicate that integration of digital logic devices and memristors could open the way for nonvolatile computation with applications in small platforms that rely on intermittent power sources. This demonstrated feasibility of tight integration of memristors with CMOS (complementary metal-oxide-semiconductor) circuitry challenges the traditional memory hierarchy, in which nonvolatile memory is only available as a large, slow, monolithic block at the bottom of the hierarchy. In contrast, the nonvolatile, memristor-based memory cell can be fast, fine-grained and small, and is compatible with conventional CMOS electronics. This threatens to upset the traditional memory hierarchy, and may open up new architectural possibilities beyond it.

摘要

忆阻器器件表现出一种动态电导状态,这种状态取决于激励历史,可以通过存储不同的电导状态来作为非易失性存储元件。我们描述了一种非易失性同步触发器电路的实现,该电路使用纳米尺度的忆阻器作为非易失性存储元件。对该电路的受控测试表明,在 1000 次电源丢失事件中,成功地存储和恢复了状态,错误率为 0.1%。这些结果表明,数字逻辑器件和忆阻器的集成可能为基于间歇电源的小平台上的非易失性计算开辟道路。这证明了忆阻器与 CMOS(互补金属氧化物半导体)电路的紧密集成是可行的,这对传统的存储器层次结构提出了挑战,在传统的存储器层次结构中,非易失性存储器仅作为底层的大型、低速、单片块提供。相比之下,基于非易失性忆阻器的存储单元可以是快速、细粒度和小的,并且与传统的 CMOS 电子设备兼容。这有可能打破传统的存储层次结构,并可能在其之外开辟新的架构可能性。

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