Zhang Hai-Bo, Zhang Xiang-Liang, Wang Yong, Takaoka Akio
Department of Electronic Science and Technology, Xi'an Jiaotong University, Xi'an 710049, People's Republic of China.
Rev Sci Instrum. 2007 Jan;78(1):013701. doi: 10.1063/1.2409864.
The possibility of utilizing high-energy electron tomography to characterize the micron-scale three dimensional (3D) structures of integrated circuits has been demonstrated experimentally. First, electron transmission through a tilted SiO(2) film was measured with an ultrahigh-voltage electron microscope (ultra-HVEM) and analyzed from the point of view of elastic scattering of electrons, showing that linear attenuation of the logarithmic electron transmission still holds valid for effective specimen thicknesses up to 5 microm under 2 MV accelerating voltages. Electron tomography of a micron-order thick integrated circuit specimen including the Cu/via interconnect was then tried with 3 MeV electrons in the ultra-HVEM. Serial projection images of the specimen tilted at different angles over the range of +/-90 degrees were acquired, and 3D reconstruction was performed with the images by means of the IMOD software package. Consequently, the 3D structures of the Cu lines, via and void, were revealed by cross sections and surface rendering.
利用高能电子断层扫描技术表征集成电路微米级三维(3D)结构的可能性已通过实验得到证实。首先,使用超高压电子显微镜(ultra-HVEM)测量了电子透过倾斜SiO₂薄膜的情况,并从电子弹性散射的角度进行了分析,结果表明,在2 MV加速电压下,对于有效样品厚度达5微米的情况,对数电子透射率的线性衰减仍然有效。然后,在ultra-HVEM中使用3 MeV电子对包含铜/通孔互连的微米级厚集成电路样品进行电子断层扫描。采集了样品在+/-90度范围内不同角度倾斜时的系列投影图像,并借助IMOD软件包对这些图像进行三维重建。结果,通过横截面和表面渲染揭示了铜线路、通孔和空洞的三维结构。