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具有可调节电子特性的逐层组装电荷陷阱存储器件。

Layer-by-layer assembled charge-trap memory devices with adjustable electronic properties.

作者信息

Lee Jang-Sik, Cho Jinhan, Lee Chiyoung, Kim Inpyo, Park Jeongju, Kim Yong-Mu, Shin Hyunjung, Lee Jaegab, Caruso Frank

机构信息

School of Advanced Materials Engineering, Kookmin University, Jeongneung-dong, Seongbuk-gu, Seoul 136-702, Korea.

出版信息

Nat Nanotechnol. 2007 Dec;2(12):790-5. doi: 10.1038/nnano.2007.380. Epub 2007 Dec 2.

Abstract

We describe a versatile approach for preparing flash memory devices composed of polyelectrolyte/gold nanoparticle multilayer films. Anionic gold nanoparticles were used as the charge storage elements, and poly(allylamine)/poly(styrenesulfonate) multilayers deposited onto hafnium oxide (HfO2)-coated silicon substrates formed the insulating layers. The top contact was formed by depositing HfO2 and platinum. In this study, we investigated the effect of increasing the number of polyelectrolyte and gold nanoparticle layers on memory performance, including the size of the memory window (the critical voltage difference between the 'programmed' and 'erased' states of the devices) and programming speed. We observed a maximum memory window of about 1.8 V, with a stored electron density of 4.2 x 1012 cm-2 in the gold nanoparticle layers, when the devices consist of three polyelectrolyte/gold nanoparticle layers. The reported approach offers new opportunities to prepare nanostructured polyelectrolyte/gold nanoparticle-based memory devices with tailored performance.

摘要

我们描述了一种制备由聚电解质/金纳米颗粒多层膜组成的闪存器件的通用方法。阴离子金纳米颗粒用作电荷存储元件,沉积在氧化铪(HfO2)涂层硅衬底上的聚(烯丙胺)/聚(苯乙烯磺酸盐)多层膜形成绝缘层。顶部接触通过沉积HfO2和铂形成。在本研究中,我们研究了增加聚电解质和金纳米颗粒层数对存储性能的影响,包括存储窗口的大小(器件“编程”和“擦除”状态之间的临界电压差)和编程速度。当器件由三层聚电解质/金纳米颗粒层组成时,我们观察到最大存储窗口约为1.8 V,金纳米颗粒层中的存储电子密度为4.2×1012 cm-2。所报道的方法为制备具有定制性能的基于纳米结构聚电解质/金纳米颗粒的存储器件提供了新的机会。

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