Department of Chemical Engineering, Indian Institute of Science, Bangalore, 560012, India.
Nanoscale. 2011 Nov;3(11):4575-9. doi: 10.1039/c1nr10884k. Epub 2011 Oct 11.
We propose robust and scalable processes for the fabrication of floating gate devices using ordered arrays of 7 nm size gold nanoparticles as charge storage nodes. The proposed strategy can be readily adapted for fabricating next generation (sub-20 nm node) non-volatile memory devices.
我们提出了使用有序排列的 7nm 大小的金纳米粒子作为电荷存储节点制造浮栅器件的稳健且可扩展的工艺。所提出的策略可以很容易地适应制造下一代（20nm 以下节点）非易失性存储器件。
