Fortuna Seth A, Wen Jianguo, Chun Ik Su, Li Xiuling
Department of Electrical and Computer Engineering, Micro and Nanotechnology Laboratory, Frederick-Seitz Materials Research Laboratory, University of Illinois at Urbana-Champaign, Urbana, Illinois 61801, USA.
Nano Lett. 2008 Dec;8(12):4421-7. doi: 10.1021/nl802331m.
We report the controlled growth of planar GaAs semiconductor nanowires on (100) GaAs substrates using atmospheric pressure metalorganic chemical vapor deposition with Au as catalyst. These nanowires with uniform diameters are self-aligned in <110> direction in the plane of (100). The dependence of planar nanowire morphology and growth rate as a function of growth temperature provides insights into the growth mechanism and identified an ideal growth window of 470 +/- 10 degrees C for the formation of such planar geometry. Transmission electron microscopy images reveal clear epitaxial relationship with the substrate along the nanowire axial direction, and the reduction of twinning defect density by about 3 orders of magnitude compared to <111> III-V semiconductor nanowires. In addition, using the concept of sacrificial layers and elevation of Au catalyst modulated by growth condition, we demonstrate for the first time a large area direct transfer process for nanowires formed by a bottom-up approach that can maintain both the position and alignment. The planar geometry and extremely low level of crystal imperfection along with the transferability could potentially lead to highly integrated III-V nanoelectronic and nanophotonic devices on silicon and flexible substrates.
我们报道了利用以金为催化剂的常压金属有机化学气相沉积法,在(100)砷化镓衬底上可控生长平面砷化镓半导体纳米线。这些直径均匀的纳米线在(100)平面内沿<110>方向自对准。平面纳米线形态和生长速率随生长温度的变化关系为生长机制提供了见解,并确定了形成这种平面几何形状的理想生长窗口为470±10℃。透射电子显微镜图像显示,沿纳米线轴向与衬底存在清晰的外延关系,与<111> III-V族半导体纳米线相比,孪晶缺陷密度降低了约3个数量级。此外,利用牺牲层的概念以及通过生长条件调节金催化剂的高度,我们首次展示了一种用于通过自下而上方法形成的纳米线的大面积直接转移工艺,该工艺可以保持位置和对准。平面几何形状、极低的晶体缺陷水平以及可转移性可能会促成在硅和柔性衬底上制造高度集成的III-V族纳米电子和纳米光子器件。