用于神经植入的自适应分辨率模数转换器阵列
Adaptive resolution ADC array for neural implant.
作者信息
O'Driscoll Stephen, Meng Teresa H
机构信息
Department of Electrical Engineering, Stanford University, Stanford, CA 94305, USA.
出版信息
Annu Int Conf IEEE Eng Med Biol Soc. 2009;2009:1053-6. doi: 10.1109/IEMBS.2009.5335410.
This paper describes an ADC array for an implantable prosthetic processor which digitizes neural signals sensed by a microelectrode array. The ADC array consists of 96 variable resolution ADC base cells. The base ADC has been implemented in 0.13 microm CMOS as a 100kS/s SAR ADC whose resolution can be varied from 3 to 8-bits with corresponding power consumption of 0.23 microW to 0.90 microW achieving an ENOB of 7.8 at the 8-bit setting. The resolution of each ADC cell in the array is varied according to neural data content of the signal from the corresponding electrode. Resolution adaptation reduces power consumption by a factor of 2.3 whilst maintaining an effective 7.8-bit resolution across all channels.
本文描述了一种用于植入式假肢处理器的模数转换器（ADC）阵列，该阵列可将微电极阵列感测到的神经信号数字化。该ADC阵列由96个可变分辨率ADC基本单元组成。基本ADC已采用0.13微米互补金属氧化物半导体（CMOS）工艺实现为100kS/s逐次逼近型寄存器（SAR）ADC，其分辨率可在3至8位之间变化，相应功耗为0.23微瓦至0.90微瓦，在8位设置下实现了7.8的有效位数（ENOB）。阵列中每个ADC单元的分辨率根据来自相应电极的信号的神经数据内容而变化。分辨率自适应将功耗降低了2.3倍，同时在所有通道上保持有效的7.8位分辨率。
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