Zhang Jie, Mitra Srinjoy, Suo Yuanming, Cheng Andrew, Xiong Tao, Michon Frederic, Welkenhuysen Marleen, Kloosterman Fabian, Chin Peter S, Hsiao Steven, Tran Trac D, Yazicioglu Firat, Etienne-Cummings Ralph
Department of Electrical and Computer Engineering, Johns Hopkins University, Baltimore, USA.
J Neural Eng. 2015 Jun;12(3):036005. doi: 10.1088/1741-2560/12/3/036005. Epub 2015 Apr 15.
This paper describes a low power closed-loop compressive sensing (CS) based neural recording system. This system provides an efficient method to reduce data transmission bandwidth for implantable neural recording devices. By doing so, this technique reduces a majority of system power consumption which is dissipated at data readout interface. The design of the system is scalable and is a viable option for large scale integration of electrodes or recording sites onto a single device.
The entire system consists of an application-specific integrated circuit (ASIC) with 4 recording readout channels with CS circuits, a real time off-chip CS recovery block and a recovery quality evaluation block that provides a closed feedback to adaptively adjust compression rate. Since CS performance is strongly signal dependent, the ASIC has been tested in vivo and with standard public neural databases.
Implemented using efficient digital circuit, this system is able to achieve >10 times data compression on the entire neural spike band (500-6KHz) while consuming only 0.83uW (0.53 V voltage supply) additional digital power per electrode. When only the spikes are desired, the system is able to further compress the detected spikes by around 16 times. Unlike other similar systems, the characteristic spikes and inter-spike data can both be recovered which guarantes a >95% spike classification success rate. The compression circuit occupied 0.11mm(2)/electrode in a 180nm CMOS process. The complete signal processing circuit consumes <16uW/electrode.
Power and area efficiency demonstrated by the system make it an ideal candidate for integration into large recording arrays containing thousands of electrode. Closed-loop recording and reconstruction performance evaluation further improves the robustness of the compression method, thus making the system more practical for long term recording.
本文介绍了一种基于低功耗闭环压缩感知(CS)的神经记录系统。该系统提供了一种有效的方法来降低植入式神经记录设备的数据传输带宽。通过这样做,该技术减少了在数据读出接口处耗散的大部分系统功耗。该系统的设计具有可扩展性,是将电极或记录位点大规模集成到单个设备上的可行选择。
整个系统由一个具有4个带CS电路的记录读出通道的专用集成电路(ASIC)、一个实时片外CS恢复模块和一个恢复质量评估模块组成,该评估模块提供闭环反馈以自适应调整压缩率。由于CS性能强烈依赖于信号,因此该ASIC已在体内和标准公共神经数据库中进行了测试。
该系统采用高效数字电路实现,能够在整个神经尖峰频段(500 - 6KHz)实现>10倍的数据压缩,同时每个电极仅消耗0.83μW(电源电压0.53V)的额外数字功率。当只需要尖峰时,该系统能够将检测到的尖峰进一步压缩约16倍。与其他类似系统不同,特征尖峰和尖峰间数据都可以恢复,这保证了>95%的尖峰分类成功率。在180nm CMOS工艺中,压缩电路每电极占用0.11mm²。完整的信号处理电路每电极消耗<16μW。
该系统展示的功率和面积效率使其成为集成到包含数千个电极的大型记录阵列中的理想候选者。闭环记录和重建性能评估进一步提高了压缩方法的鲁棒性,从而使该系统更适用于长期记录。