Nie Z D, Wang L, Chen W G, Zhang T, Zhang Y T
Institute of Biomedical and Health Engineering (IBHE) Shenzhen Institute of Advanced Technology (SIAT).
Annu Int Conf IEEE Eng Med Biol Soc. 2009;2009:2559-62. doi: 10.1109/IEMBS.2009.5335295.
A low power biomedical digital signal processor ASIC based on hardware and software codesign methodology was presented in this paper. The codesign methodology was used to achieve higher system performance and design flexibility. The hardware implementation included a low power 32bit RISC CPU ARM7TDMI, a low power AHB-compatible bus, and a scalable digital co-processor that was optimized for low power Fast Fourier Transform (FFT) calculations. The co-processor could be scaled for 8-point, 16-point and 32-point FFTs, taking approximate 50, 100 and 150 clock circles, respectively. The complete design was intensively simulated using ARM DSM model and was emulated by ARM Versatile platform, before conducted to silicon. The multi-million-gate ASIC was fabricated using SMIC 0.18 microm mixed-signal CMOS 1P6M technology. The die area measures 5,000 microm x 2,350 microm. The power consumption was approximately 3.6 mW at 1.8 V power supply and 1 MHz clock rate. The power consumption for FFT calculations was less than 1.5 % comparing with the conventional embedded software-based solution.
本文介绍了一种基于硬件和软件协同设计方法的低功耗生物医学数字信号处理器专用集成电路。该协同设计方法用于实现更高的系统性能和设计灵活性。硬件实现包括一个低功耗32位RISC CPU ARM7TDMI、一个低功耗AHB兼容总线以及一个针对低功耗快速傅里叶变换（FFT）计算进行优化的可扩展数字协处理器。该协处理器可扩展用于8点、16点和32点FFT，分别大约需要50、100和150个时钟周期。在进行流片之前，使用ARM DSM模型对整个设计进行了密集模拟，并通过ARM通用平台进行了仿真。该数百万门专用集成电路采用中芯国际0.18微米混合信号CMOS 1P6M技术制造。芯片面积为5000微米×2350微米。在1.8V电源电压和1MHz时钟频率下，功耗约为3.6mW。与传统的基于嵌入式软件的解决方案相比，FFT计算的功耗小于1.5%。
