Department of Materials Science and Engineering, Yonsei University, Seoul 120-749, Korea.
Nano Lett. 2011 Jan 12;11(1):138-44. doi: 10.1021/nl103094e. Epub 2010 Nov 29.
We demonstrate significantly improved performance of a nonvolatile polymeric ferroelectric field effect transistor (FeFET) memory using nanoscopic confinement of poly(vinylidene fluoride-co-trifluoroethylene) (PVDF-TrFE) within self-assembled organosilicate (OS) lamellae. Periodic OS lamellae with 30 nm in width and 50 nm in periodicity were templated using block copolymer self-assembly. Confined crystallization of PVDF-TrFE not only significantly reduces gate leakage current but also facilitates ferroelectric polarization switching. These benefits are due to the elimination of structural defects and the development of an effective PVDF-TrFE crystal orientation through nanoconfinement. A bottom gate FeFET fabricated using a single-crystalline triisopropylsilylethynyl pentacene channel and PVDF-TrFE/OS hybrid gate insulator shows characteristic source-drain current hysteresis that is fully saturated at a programming voltage of ±8 V with an ON/OFF current ratio and a data retention time of approximately 10(2) and 2 h, respectively.
我们展示了使用纳米尺度的聚(偏二氟乙烯-共-三氟乙烯)(PVDF-TrFE)在自组装有机硅(OS)层内受限,显著提高了非易失性聚合物铁电场效应晶体管(FeFET)存储器的性能。使用嵌段共聚物自组装,周期性的 OS 层具有 30nm 的宽度和 50nm 的周期性。受限结晶的 PVDF-TrFE 不仅显著降低了栅漏电流,而且有利于铁电极化开关。这些好处归因于结构缺陷的消除和通过纳米限制形成有效 PVDF-TrFE 晶体取向。使用单晶三异丙基硅乙炔基五苯通道和 PVDF-TrFE/OS 混合栅极绝缘体制造的底栅 FeFET 显示出源漏电流滞后的特征,在编程电压为±8V 时完全饱和,导通/关断电流比约为 10(2),数据保持时间约为 2 小时。