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通过纳米压印和蚀刻对直径小于40纳米且高宽比大于50:1的硅柱阵列进行晶圆级图案化。

Wafer-scale patterning of sub-40 nm diameter and high aspect ratio (>50:1) silicon pillar arrays by nanoimprint and etching.

作者信息

Morton Keith J, Nieberg Gregory, Bai Shufeng, Chou Stephen Y

机构信息

Nanostructure Laboratory, Department of Electrical Engineering, Princeton University, Princeton, NJ 08544, USA.

出版信息

Nanotechnology. 2008 Aug 27;19(34):345301. doi: 10.1088/0957-4484/19/34/345301. Epub 2008 Jul 15.

Abstract

We demonstrate wide-area fabrication of sub-40 nm diameter, 1.5 µm tall, high aspect ratio silicon pillar arrays with straight sidewalls by combining nanoimprint lithography (NIL) and deep reactive ion etching (DRIE). Imprint molds were used to pre-pattern nanopillar positions precisely on a 200 nm square lattice with long range order. The conventional DRIE etching process was modified and optimized with reduced cycle times and gas flows to achieve vertical sidewalls; with such techniques the pillar sidewall roughness can be reduced below 8 nm (peak-to-peak). In some cases, sub-50 nm diameter pillars, 3 µm tall, were fabricated to achieve aspect ratios greater than 60:1.

摘要

我们通过结合纳米压印光刻(NIL)和深反应离子刻蚀(DRIE)技术,展示了大面积制造直径小于40纳米、高度为1.5微米、具有直侧壁的高纵横比硅柱阵列。压印模具用于在具有长程有序的200纳米正方形晶格上精确预图案化纳米柱位置。对传统的DRIE蚀刻工艺进行了改进和优化,减少了循环时间和气体流量以实现垂直侧壁;采用这些技术,柱侧壁粗糙度可降低至8纳米以下(峰峰值)。在某些情况下,制造了直径小于50纳米、高度为3微米的柱,以实现大于60:1的纵横比。

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