Yamamura Kazuya, Ueda Kazuaki, Hosoda Mao, Zettsu Nobuyuki
Research Center for Ultra-precision Science and Technology, Graduate School of Engineering, Osaka University, Yamadaoka 2-1, Suita, Osaka 565-0871, Japan.
J Nanosci Nanotechnol. 2011 Apr;11(4):2910-5. doi: 10.1166/jnn.2011.3922.
Silicon-on-insulator (SOI) wafers are promising semiconductor materials for high-speed LSIs, low-power-consumption electric devices and micro electro mechanical systems (MEMS). The thickness distribution of an SOI causes the variation of threshold voltage in electronic devices manufactured on the SOI wafer. The thickness distribution of a thin SOI, which is manufactured by applying a smart cut technique, is comparatively uniform. On the other hand, a thick SOI has a large thickness distribution because a bonded wafer is thinned by conventional grinding and polishing. For a thick SOI wafer with a thickness of 1 microm, it is required that the tolerance of thickness variation is less than 50 nm. However, improving the thickness uniformity of a thick SOI layer to a tolerance of +/- 5% is difficult by conventional machining because of the fundamental limitations of these techniques. We have developed numerically controlled local wet etching (NC-LWE) technique as a novel deterministic subaperture figuring and finishing technique, which utilizes a localized chemical reaction between the etchant and the surface of the workpiece. We demonstrated an improvement in the thickness distribution of a thick SOI by NC-LWE using an HF/HNO3 mixture, and thickness variation improved from 480 nm to 200 nm within a diameter of 170 mm.
绝缘体上硅（SOI）晶圆是用于高速大规模集成电路、低功耗电子器件和微机电系统（MEMS）的很有前景的半导体材料。SOI的厚度分布会导致在SOI晶圆上制造的电子器件中阈值电压的变化。通过应用智能剥离技术制造的薄SOI的厚度分布相对均匀。另一方面，厚SOI具有较大的厚度分布，因为键合晶圆是通过传统的研磨和抛光减薄的。对于厚度为1微米的厚SOI晶圆，要求厚度变化的公差小于50纳米。然而，由于这些技术的基本局限性，通过传统加工将厚SOI层的厚度均匀性提高到±5%的公差是困难的。我们已经开发了数控局部湿法蚀刻（NC-LWE）技术，作为一种新颖的确定性子孔径加工和精整技术，该技术利用蚀刻剂与工件表面之间的局部化学反应。我们展示了使用HF/HNO3混合物通过NC-LWE改善厚SOI的厚度分布，并且在直径170毫米范围内厚度变化从480纳米改善到200纳米。
