Department of Polymer Science and Engineering, University of Massachusetts-Amherst, 120 Governors Drive, Amherst, Massachusetts 01003, United States.
ACS Nano. 2012 Feb 28;6(2):1188-94. doi: 10.1021/nn203847r. Epub 2012 Jan 30.
Floating gate memory devices were fabricated using well-ordered gold nanoparticle/block copolymer hybrid films as the charge trapping layers, SiO(2) as the dielectric layer, and poly(3-hexylthiophene) as the semiconductor layer. The charge trapping layer was prepared via self-assembly. The addition of Au nanoparticles that selectively hydrogen bond with pyridine in a poly(styrene-b-2-vinyl pyridine) block copolymer yields well-ordered hybrid materials at Au nanoparticle loadings up to 40 wt %. The characteristics of the memory window were tuned by simple control of the Au nanoparticle concentration. This approach enables the fabrication of well-ordered charge storage layers by solution processing, which is extendable for the fabrications of large area and high density devices via roll-to-roll processing.
采用有序的金纳米粒子/嵌段共聚物杂化薄膜作为电荷俘获层、SiO2 作为介电层、聚(3-己基噻吩)作为半导体层，制备浮栅存储器件。电荷俘获层通过自组装制备。在聚(苯乙烯-b-2-乙烯基吡啶)嵌段共聚物中加入与吡啶选择性氢键结合的 Au 纳米粒子，在 Au 纳米粒子负载量高达 40wt%时，得到有序的杂化材料。通过简单控制 Au 纳米粒子的浓度来调整存储窗口的特性。这种方法可以通过溶液处理制备有序的电荷存储层，通过卷对卷工艺可以扩展到大面积和高密度器件的制造。
