Department of Computer Architecture and Technology, ETS Computer Engineering and Telecommunications, University of Granada, C/ Periodista Daniel Saucedo s/n, E18071 Granada, Spain.
Sensors (Basel). 2012;12(1):585-611. doi: 10.3390/s120100585. Epub 2012 Jan 5.
Background subtraction is considered the first processing stage in video surveillance systems, and consists of determining objects in movement in a scene captured by a static camera. It is an intensive task with a high computational cost. This work proposes an embedded novel architecture on FPGA which is able to extract the background on resource-limited environments and offers low degradation (produced because of the hardware-friendly model modification). In addition, the original model is extended in order to detect shadows and improve the quality of the segmentation of the moving objects. We have analyzed the resource consumption and performance in Spartan3 Xilinx FPGAs and compared to others works available on the literature, showing that the current architecture is a good trade-off in terms of accuracy, performance and resources utilization. With less than a 65% of the resources utilization of a XC3SD3400 Spartan-3A low-cost family FPGA, the system achieves a frequency of 66.5 MHz reaching 32.8 fps with resolution 1,024 × 1,024 pixels, and an estimated power consumption of 5.76 W.
背景减除被认为是视频监控系统的第一个处理阶段，它包括确定由静态摄像机捕获的场景中运动的物体。这是一项密集型任务，计算成本很高。这项工作提出了一种基于 FPGA 的嵌入式新型架构，能够在资源有限的环境中提取背景，并且提供低降级（由于硬件友好型模型修改而产生）。此外，还扩展了原始模型，以检测阴影并提高运动对象分割的质量。我们已经分析了 Spartan3 Xilinx FPGAs 中的资源消耗和性能，并与文献中可用的其他工作进行了比较，表明当前的架构在准确性、性能和资源利用率方面是一个很好的折衷方案。该系统在 XC3SD3400 Spartan-3A 低成本系列 FPGA 中不到 65%的资源利用率下，实现了 66.5MHz 的频率，分辨率为 1024×1024 像素时帧率为 32.8fps，估计功耗为 5.76W。
