Integrated Nanotechnology Lab, Electrical Engineering Program, Computer Electrical Mathematical Science and Engineering Division, King Abdullah University of Science and Technology, Thuwal 23955-6900, Saudi Arabia.
ACS Nano. 2013 Jul 23;7(7):5818-23. doi: 10.1021/nn400796b. Epub 2013 Jun 20.
Utilization of graphene may help realize innovative low-power replacements for III-V materials based high electron mobility transistors while extending operational frequencies closer to the THz regime for superior wireless communications, imaging, and other novel applications. Device architectures explored to date suffer a fundamental performance roadblock due to lack of compatible deposition techniques for nanometer-scale dielectrics required to efficiently modulate graphene transconductance (gm) while maintaining low gate capacitance-voltage product (CgsVgs). Here we show integration of a scaled (10 nm) high-κ gate dielectric aluminum oxide (Al2O3) with an atmospheric pressure chemical vapor deposition (APCVD)-derived graphene channel composed of multiple 0.25 μm stripes to repeatedly realize room-temperature mobility of 11,000 cm(2)/V·s or higher. This high performance is attributed to the APCVD graphene growth quality, excellent interfacial properties of the gate dielectric, conductivity enhancement in the graphene stripes due to low tox/Wgraphene ratio, and scaled high-κ dielectric gate modulation of carrier density allowing full actuation of the device with only ±1 V applied bias. The superior drive current and conductance at Vdd = 1 V compared to other top-gated devices requiring undesirable seed (such as aluminum and poly vinyl alcohol)-assisted dielectric deposition, bottom gate devices requiring excessive gate voltage for actuation, or monolithic (nonstriped) channels suggest that this facile transistor structure provides critical insight toward future device design and process integration to maximize CVD-based graphene transistor performance.
利用石墨烯可能有助于实现基于 III-V 材料的高电子迁移率晶体管的创新低功率替代品，同时将工作频率扩展到太赫兹范围，以实现卓越的无线通信、成像和其他新颖应用。迄今为止探索的器件结构由于缺乏用于有效调制石墨烯跨导（gm）的纳米级介电常数的兼容沉积技术而受到基本性能障碍的限制，同时保持低栅极电容-电压乘积（CgsVgs）。在这里，我们展示了缩放（10nm）高κ栅极电介质氧化铝（Al2O3）与常压化学气相沉积（APCVD）衍生的石墨烯沟道的集成，该沟道由多个 0.25μm 条纹组成，可重复实现室温下 11,000cm2/V·s 或更高的迁移率。这种高性能归因于 APCVD 石墨烯生长质量、栅极电介质的优异界面特性、由于 tox/Wgraphene 比值低而导致石墨烯条纹中的电导率增强，以及缩放的高κ介电栅极对载流子密度的调制，允许仅施加±1V 偏置即可完全激活器件。与其他需要不理想的种子（如铝和聚乙烯醇）辅助介电沉积的顶栅器件、需要过量栅极电压才能激活的底栅器件，或需要采用复杂工艺才能实现的单片（非条纹）沟道相比，在 Vdd = 1V 时，该器件具有优越的驱动电流和导通电阻，这表明这种简单的晶体管结构为未来的器件设计和工艺集成提供了关键的见解，以最大限度地提高基于 CVD 的石墨烯晶体管性能。
