Texas Instruments Incorpoarted, Dallas, TX 75266, USA.
IEEE Trans Biomed Circuits Syst. 2012 Apr;6(2):142-55. doi: 10.1109/TBCAS.2011.2179544.
The Time Machine (TM) is a spike-based computation architecture that represents synaptic weights in time. This choice of weight representation allows the use of virtual synapses, providing an excellent tradeoff in terms of flexibility, arbitrary weight connections and hardware usage compared to dedicated synapse architectures. The TM supports an arbitrary number of synapses and is limited only by the number of simultaneously active synapses to each neuron. SpikeSim, a behavioral hardware simulator for the architecture, is described along with example algorithms for edge detection and objection recognition. The TM can implement traditional spike-based processing as well as recently developed time mode operations where step functions serve as the input and output of each neuron block. A custom hybrid digital/analog implementation and a fully digital realization of the TM are discussed. An analog chip with 32 neurons, 1024 synapses and an address event representation (AER) block has been fabricated in 0.5 μm technology. A fully digital field-programmable gate array (FPGA)-based implementation of the architecture has 6,144 neurons and 100,352 simultaneously active synapses. Both implementations utilize a digital controller for routing spikes that can process up to 34 million synapses per second.
时间机器 (TM) 是一种基于尖峰的计算架构，它在时间上表示突触权重。这种权重表示的选择允许使用虚拟突触，与专用突触架构相比，在灵活性、任意权重连接和硬件使用方面提供了极好的权衡。TM 支持任意数量的突触，并且仅受每个神经元同时激活的突触数量限制。描述了 SpikeSim，这是一种针对该架构的行为硬件模拟器，并提供了边缘检测和对象识别的示例算法。TM 可以实现传统的基于尖峰的处理，以及最近开发的时间模式操作，其中阶跃函数作为每个神经元块的输入和输出。讨论了定制的混合数字/模拟实现和 TM 的全数字实现。已经在 0.5 μm 技术中制造了具有 32 个神经元、1024 个突触和地址事件表示 (AER) 块的模拟芯片。该架构的全数字现场可编程门阵列 (FPGA) 实现具有 6144 个神经元和 100352 个同时激活的突触。这两种实现都利用了用于路由尖峰的数字控制器，该控制器每秒可处理多达 3400 万个突触。
