Center for Integrated Systems and Department of Electrical Engineering, Stanford University, Stanford, CA 94305, USA.
Nanotechnology. 2013 Nov 22;24(46):465201. doi: 10.1088/0957-4484/24/46/465201. Epub 2013 Oct 22.
The vertical scaling for the multi-layer stacked 3D vertical resistive random access memory (RRAM) cross-point array is investigated. The thickness of the multi-layer stack for a 3D RRAM is a key factor for determining the storage density. A vertical RRAM cell with plane electrode thickness (tm) scaled down to 5 nm, aiming to minimize 3D stack height, is experimentally demonstrated. An improvement factor of 5 in device density can be achieved as compared to a previous demonstration using a 22 nm thick plane electrode. It is projected that 37 layers can be stacked for a lithographic half-pitch (F) = 26 nm and total thickness of one stack (T) = 21 nm, delivering a bit density of 72.8 nm(2)/cell.
对多层堆叠 3D 垂直电阻式随机存取存储器 (RRAM) 交叉点阵列的垂直扩展进行了研究。多层堆叠的厚度是决定存储密度的关键因素。实验演示了一种具有平面电极厚度 (tm) 缩小至 5nm 的垂直 RRAM 单元，旨在最小化 3D 堆叠高度。与之前使用 22nm 厚平面电极的演示相比，器件密度提高了 5 倍。预计可以堆叠 37 层，对于光刻半间距 (F) = 26nm 和一个堆叠的总厚度 (T) = 21nm，可以实现 72.8nm(2)/cell 的位密度。
