Oh Jinho, Na Heedo, Park Sunghoon, Sohn Hyunchul
Department of Materials Science and Engineering, Yonsei University, Seoul 120-749, Korea.
J Nanosci Nanotechnol. 2013 Sep;13(9):6413-5. doi: 10.1166/jnn.2013.7625.
The electrical characteristics of tunnel barrier engineered-charge trap flash (TBE-CTF) memory devices with junctionless (JL) source and drain (S/D) were investigated. The JL structure is composed of an n(+)-poly-Si based ultra-thin channel and S/D with identical doping concentrations. The band engineered Hf-silicate/Al2O3 tunnel barrier stack was applied to a JL-TBE-CTF memory device in order to enhance the field sensitivity. The Hf-silicate/Al2O3 tunnel barrier, HfO2 trap layer, and Al2O3 blocking layer were deposited by atomic layer deposition. The fabricated device exhibited a large memory window of 9.43 V, as well as high programming and erasing speeds. Moreover, it also showed adequate retention times and endurance properties. Hence, the JL-TBE-CTF memory (which has a low process complexity) is expected to be an appropriate structure for 3D stacked ultra-high density memory applications.
研究了具有无结(JL)源极和漏极(S/D)的隧道势垒工程电荷陷阱闪存(TBE-CTF)存储器件的电学特性。JL结构由基于n(+) - 多晶硅的超薄沟道和具有相同掺杂浓度的S/D组成。为了提高场灵敏度,将能带工程化的Hf - 硅酸盐/Al2O3隧道势垒堆叠应用于JL - TBE - CTF存储器件。通过原子层沉积法沉积Hf - 硅酸盐/Al2O3隧道势垒、HfO2陷阱层和Al2O3阻挡层。所制备的器件表现出9.43 V的大存储窗口,以及高编程和擦除速度。此外,它还显示出足够的保持时间和耐久性。因此,具有低工艺复杂度的JL - TBE - CTF存储器有望成为3D堆叠超高密度存储器应用的合适结构。