Yoo Chan Ho, Ko Seong Hoon, Kim Tae Whan
Department of Electronics and Computer Engineering, Hanyang University, Seoul 133-791, Korea.
J Nanosci Nanotechnol. 2013 Sep;13(9):6463-6. doi: 10.1166/jnn.2013.7617.
The electrical bistabilities and the memory stabilities of organic bistable devices (OBDs) based on multi-core-shell CdSe/CdS/ZnS nanoparticles embedded in a polystyrene (PS) layer fabricated by using a spin-coating method were investigated. The current density-voltage (J-V) curves for the Al/multi-core-shell CdSe/CdS/ZnS nanoparticles embedded in PS layer/WO3/indium-tin-oxide (ITO) devices showed current bistability with a maximum ON/OFF ratio of 1 x 10(3), which was much larger than that of a device without a WO3 layer. The leakage current of the OBDs was decreased by insertion of the WO3 layer between the PS layer containing nanoparticles and the ITO electrode, resulting in a decrease in the current deviation between the experimental and the simulated currents in the low-voltage region. The effects of the WO3 blocking layer on the electrical characteristics of the OBDs were investigated, and the carrier transport mechanisms for the OBDs were described on the basis of the J-V experimental data and theoretical results.
研究了基于通过旋涂法制备的嵌入聚苯乙烯（PS）层中的多核壳CdSe/CdS/ZnS纳米颗粒的有机双稳器件（OBD）的电双稳性和记忆稳定性。Al/嵌入PS层中的多核壳CdSe/CdS/ZnS纳米颗粒/WO3/氧化铟锡（ITO）器件的电流密度-电压（J-V）曲线显示出电流双稳性，最大开/关比为1×10³，这比没有WO3层的器件大得多。通过在包含纳米颗粒的PS层和ITO电极之间插入WO3层，OBD的漏电流降低，导致低电压区域实验电流和模拟电流之间的电流偏差减小。研究了WO3阻挡层对OBD电学特性的影响，并根据J-V实验数据和理论结果描述了OBD的载流子传输机制。
