School of Materials Science and Engineering, Georgia Institute of Technology . 771 Ferst Drive, Atlanta, Georgia 30332, United States.
ACS Appl Mater Interfaces. 2014 Oct 8;6(19):16782-91. doi: 10.1021/am504046b. Epub 2014 Sep 19.
In this work, a novel wet silicon (Si) etching method, electric bias-attenuated metal-assisted chemical etching (EMaCE), is demonstrated to be readily available for three-dimensional (3D) electronic integration, microelectromechinal systems, and a broad range of 3D electronic components with low cost. On the basis of the traditional metal-assisted chemical etching process, an electric bias was applied to the Si substrate in EMaCE. The 3D geometry of the etching profile was effectively controlled by the bias in a real-time manner. The reported method successfully fabricated an array of over 10 000 vertical holes with diameters of 28 μm on 1 cm(2) silicon chips at a rate of up to 11 μm/min. The sidewall roughness was kept below 50 nm, and a high aspect ratio of over 10:1 was achieved. The 3D geometry could be attenuated by the variable applied bias in real time. Vertical deep etching was realized on (100)-, (111)-Si, and polycrystalline Si substrates. Complex features with lateral dimensions of 0.8-500 μm were also fabricated with submicron accuracy.
在这项工作中,展示了一种新颖的湿硅(Si)蚀刻方法,即偏压衰减金属辅助化学蚀刻(EMaCE),该方法可用于三维(3D)电子集成、微机电系统以及具有低成本的广泛 3D 电子组件。在传统的金属辅助化学蚀刻工艺的基础上,在 EMaCE 中向 Si 衬底施加偏压。通过偏压,可以实时有效地控制蚀刻轮廓的 3D 几何形状。所报道的方法成功地在 1cm(2)硅片上以高达 11μm/min 的速率制造了直径为 28μm 的超过 10000 个垂直孔的阵列。侧壁粗糙度保持在 50nm 以下,高纵横比超过 10:1。3D 几何形状可以通过实时施加的可变偏压来衰减。在(100)-、(111)-Si 和多晶硅衬底上实现了垂直深蚀刻。还以亚微米精度制造了具有 0.8-500μm 横向尺寸的复杂特征。