用于实时脑电图系统的16通道在线递归独立成分分析处理器的高效专用集成电路实现。
An efficient ASIC implementation of 16-channel on-line recursive ICA processor for real-time EEG system.
作者信息
Fang Wai-Chi, Huang Kuan-Ju, Chou Chia-Ching, Chang Jui-Chung, Cauwenberghs Gert, Jung Tzyy-Ping
出版信息
Annu Int Conf IEEE Eng Med Biol Soc. 2014;2014:3849-52. doi: 10.1109/EMBC.2014.6944463.
This is a proposal for an efficient very-large-scale integration (VLSI) design, 16-channel on-line recursive independent component analysis (ORICA) processor ASIC for real-time EEG system, implemented with TSMC 40 nm CMOS technology. ORICA is appropriate to be used in real-time EEG system to separate artifacts because of its highly efficient and real-time process features. The proposed ORICA processor is composed of an ORICA processing unit and a singular value decomposition (SVD) processing unit. Compared with previous work [1], this proposed ORICA processor has enhanced effectiveness and reduced hardware complexity by utilizing a deeper pipeline architecture, shared arithmetic processing unit, and shared registers. The 16-channel random signals which contain 8-channel super-Gaussian and 8-channel sub-Gaussian components are used to analyze the dependence of the source components, and the average correlation coefficient is 0.95452 between the original source signals and extracted ORICA signals. Finally, the proposed ORICA processor ASIC is implemented with TSMC 40 nm CMOS technology, and it consumes 15.72 mW at 100 MHz operating frequency.
这是一份关于高效超大规模集成电路（VLSI）设计的提案，即用于实时脑电图（EEG）系统的16通道在线递归独立成分分析（ORICA）处理器专用集成电路（ASIC），采用台积电40纳米互补金属氧化物半导体（CMOS）技术实现。由于其高效和实时处理特性，ORICA适用于实时EEG系统以分离伪迹。所提出的ORICA处理器由一个ORICA处理单元和一个奇异值分解（SVD）处理单元组成。与先前的工作[1]相比，该提出的ORICA处理器通过采用更深的流水线架构、共享算术处理单元和共享寄存器，提高了有效性并降低了硬件复杂度。使用包含8通道超高斯和8通道亚高斯成分的16通道随机信号来分析源成分的相关性，原始源信号与提取的ORICA信号之间的平均相关系数为0.95452。最后，所提出的ORICA处理器ASIC采用台积电40纳米CMOS技术实现，在100兆赫工作频率下功耗为15.72毫瓦。
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