Klepacki K, Pawłowski M, Szplet R
Military University of Technology, Kaliskiego 2, 00-908 Warsaw, Poland.
Rev Sci Instrum. 2015 Feb;86(2):025111. doi: 10.1063/1.4908199.
We present the design, operation, and test results of a new time interval/delay generator that provides the resolution of 0.3 ps, jitter below 10 ps (rms), and wide delay range of 10 s. The wide range has been achieved by counting periods of a reference clock while the high resolution and low jitter have been obtained through the two-time use of inner interpolation. This interpolation, based on charging of a single capacitor, provides both the precise external trigger synchronization and accurate generation of residual time interval. A combination of both processes virtually eliminates triggering indeterminacy. The jitter between the trigger and output is below 1 ps, which ensures a high performance delay. The generator is integrated in a single application specific integrated circuit chip using a standard cost-effective 0.35 μm CMOS process.
我们展示了一种新型时间间隔/延迟发生器的设计、操作及测试结果。该发生器的分辨率为0.3皮秒，抖动低于10皮秒（均方根值），延迟范围宽达10秒。宽延迟范围是通过对参考时钟的周期进行计数实现的，而高分辨率和低抖动则是通过两次使用内部插值获得的。这种基于单个电容器充电的插值方法，既提供了精确的外部触发同步，又能准确生成剩余时间间隔。这两个过程的结合几乎消除了触发不确定性。触发与输出之间的抖动低于1皮秒，确保了高性能延迟。该发生器采用标准的高性价比0.35微米互补金属氧化物半导体工艺集成在单个专用集成电路芯片中。
