Liu Jinxin, Deng Peipei, Liu Juan, Wang Ying
Microsystem and Terahertz Research Center, China Academy of Engineering Physics, Chengdu 610200, Sichuan, China.
Institute of Electronic Engineering, China Academy of Engineering Physics, Mianyang 621900, Sichuan, China.
Rev Sci Instrum. 2024 Jul 1;95(7). doi: 10.1063/5.0210810.
This paper introduces the design and implementation of a prototype Digital Delay Generator (DDG) characterized by high precision, low jitter, and a wide delay range, fully realized within a Field Programmable Gate Array (FPGA). The DDG's architecture is based on an innovative combination of an embedded time-to-digital converter (TDC) and Multi-stage Time Interpolation (MTI) delay logic. The paper explores the factors influencing delay jitter during external trigger mode and carefully selects the optimal design approach for each element. The embedded TDC, which undergoes automatic calibration, accurately measures the time difference between the arrival of an external trigger and the FPGA's internal clock signal. When paired with the MTI delay logic, this allows for highly precise control over delay durations. A key aspect of this design is its sole dependence on the FPGA's built-in resources, ensuring simplicity in implementation and adaptability to various applications. Evaluation of the prototype has shown promising results, demonstrating a delay resolution as fine as 20 ps and maintaining a low jitter of 105 ps peak-to-peak (20 ps rms) when operated in the externally triggered mode.
本文介绍了一种数字延迟发生器（DDG）原型的设计与实现，其特点是高精度、低抖动和宽延迟范围，完全在现场可编程门阵列（FPGA）中实现。DDG的架构基于嵌入式时间数字转换器（TDC）和多级时间插值（MTI）延迟逻辑的创新组合。本文探讨了外部触发模式下影响延迟抖动的因素，并为每个元件精心选择了最佳设计方法。经过自动校准的嵌入式TDC可精确测量外部触发信号到达与FPGA内部时钟信号之间的时间差。当与MTI延迟逻辑配合使用时，这允许对延迟持续时间进行高精度控制。该设计的一个关键方面是它完全依赖于FPGA的内置资源，确保了实现的简单性和对各种应用的适应性。对该原型的评估显示了有前景的结果，在外部触发模式下运行时，延迟分辨率高达20皮秒，峰峰值抖动低至105皮秒（均方根值为20皮秒）。
