Chen Zeyang, Wang Xiaohan, Zhou Ziwen, Moro Ramiro, Ma Lei
Tianjin International Center for Nanoparticles and Nanosystems, Tianjin University, 92 Weijin Road, Nankai District, Tianjin 300072, China.
Rev Sci Instrum. 2021 Feb 1;92(2):024701. doi: 10.1063/5.0030341.
Pulse delay generators are ubiquitous in laboratories to coordinate and control the timing between different devices in applications that include lasers, mass spectrometers, and other scientific instruments. The most important required characteristics are precision, to control time exactly, and low-jitter, to minimize uncertainty in experiments. Here, we introduce a new design of a high precision and low-jitter digital delay generator based on a Field Programmable Gate Array (FPGA). The final delay is composed of steps of 4.2 ns (coarse delay) with fine steps of 16 ps (fine delay). The coarse delay is generated by a 240 MHz pulse sequence from the FPGA with a 50 MHz clock. An embedded time-to-digital conversion unit is used to measure the interval between the external trigger and the clock signal, which, together with an integrated delay generator, is used to realize the fine delay. Jitter compensation is achieved through a measurement-and-feedback module. A computer interface is designed to control the system through a Nios II processor. Measurements confirm a time resolution of 16 ± 2 ps with jitter below 450 ± 20 ps (at 24 °C) with a maximum delay of 1 s. The whole system is simple in structure and low in cost.
脉冲延迟发生器在实验室中无处不在，用于协调和控制包括激光器、质谱仪及其他科学仪器在内的应用中不同设备之间的定时。最重要的所需特性是精确性，即精确控制时间，以及低抖动，以将实验中的不确定性降至最低。在此，我们介绍一种基于现场可编程门阵列（FPGA）的高精度、低抖动数字延迟发生器的新设计。最终延迟由4.2纳秒的步长（粗延迟）和16皮秒的精细步长（精细延迟）组成。粗延迟由FPGA产生的240兆赫兹脉冲序列和50兆赫兹时钟产生。一个嵌入式时间数字转换单元用于测量外部触发与时钟信号之间的间隔，该间隔与一个集成延迟发生器一起用于实现精细延迟。通过一个测量与反馈模块实现抖动补偿。设计了一个计算机接口，通过Nios II处理器控制系统。测量结果证实，在24摄氏度时，时间分辨率为16±2皮秒，抖动低于450±20皮秒，最大延迟为1秒。整个系统结构简单、成本低廉。
