Albert Anitha Juliette, Ramachandran Seshasayanan
Centre for Research, Anna University, Chennai, Tamilnadu 600025, India.
Faculty of Information and Communication Engineering, College of Engineering, Anna University, Chennai, Tamilnadu 600025, India.
ScientificWorldJournal. 2015;2015:749569. doi: 10.1155/2015/749569. Epub 2015 Mar 24.
Floating point multiplication is a critical part in high dynamic range and computational intensive digital signal processing applications which require high precision and low power. This paper presents the design of an IEEE 754 single precision floating point multiplier using asynchronous NULL convention logic paradigm. Rounding has not been implemented to suit high precision applications. The novelty of the research is that it is the first ever NULL convention logic multiplier, designed to perform floating point multiplication. The proposed multiplier offers substantial decrease in power consumption when compared with its synchronous version. Performance attributes of the NULL convention logic floating point multiplier, obtained from Xilinx simulation and Cadence, are compared with its equivalent synchronous implementation.
浮点乘法是高动态范围和计算密集型数字信号处理应用中的关键部分，这些应用需要高精度和低功耗。本文介绍了一种使用异步空约定逻辑范式设计的IEEE 754单精度浮点乘法器。为适应高精度应用，未实现舍入功能。该研究的新颖之处在于，它是首个设计用于执行浮点乘法的空约定逻辑乘法器。与同步版本相比，所提出的乘法器功耗大幅降低。将从Xilinx仿真和Cadence获得的空约定逻辑浮点乘法器的性能属性与其等效的同步实现进行了比较。
