Department of Electronics and Communication Engineering, Government College of Engineering Bargur, Krishnagiri- 635104, India.
Curr Med Imaging. 2021;17(2):276-287. doi: 10.2174/1573405616999200817101950.
FIR filter is the most widely used device in DSP applications, which is also applicable to integrate with image processing approaches. The ALU based FIR structure is applicable for various devices to increase the performance. The ALU design operation includes accumulation, subtraction, shifting, multiplication and filtering. Existing methods are designed with various multipliers like Wallace tree multiplier, DADDA multiplier, Vedic multiplier and adders like carry select adder, and carry look-ahead adder.
The main objective is to reduce the area, delay and power factors since optimum VLSI circuit is employed in this paper. By these adders and multipliers, operations are independently enabling main operations in DSP. The FIR filter is designed using a MAC unit with clock regenerative comparators.
In the field of the VLSI industry, the low power, reduced time, and area-efficient designs are mostly preferred for various applications. Adders and multipliers play a vital role in VLSI circuit designs. The recent electronics industry uses a digital filter for various real-time applications. This utilizes Finite Impulse Response (FIR) and Infinite Impulse Response (IIR) filters, here the FIR filter is most stable than IIR filter. This FIR filter indicates the impulse signal into finite form and it is used mainly in DSP processors for getting high-speed. In these two ALU and FIR circuits, the adders and multiplier block's usage is increased, it consumes much power.
The proposed research work uses the clock-gating technique for reducing power consumption. Here the latch-based clock gating technique provides an efficient result. XOR-based logic circuit reduces the design complexity and utilizes the less area. Carry save accumulator is a digital adder used for addition. It provides the two set of output, which is partial sum and carry output. The ripple carry adder uses a full adder circuit for its operation. It propagates the carry value in the last bit. In addition, the combination of CSA and RCA utilizes less area, high speed and provides the better throughput. In multiplier block, the booth multiplier algorithm is used with XOR-based logic. Here this proposed FIR filter is designed for performing image filtration of retina image. This process improves the better visualization approach inthe medical field.
Thus, the proposed ALU based FIR filter with a latch-based clock gating technique is designed and analyzed with various parameters. Here the modified adders and multipliers are proposed for the efficiency of the system. The modified carry save adder is proposed with combining ripple carry adder logic for improving the adders' performance. The enhanced booth multiplier is designed using add and shift method for reducing the numberof stages to calculate the result. This process is applied to perform image processing of the retina image. After designing the ALU based FIR filter structure in the VLSI environment, the image is loaded on the MATLAB as the .png format, then it is converted into a hex file, which is read from the Xilinx to perform filtering the process. Then the 'dataout' is converted into a binary file to obtain the result of the filtering process. The enhanced booth multiplier reduces the delay by reducing the number of stages to calculate the result. Here the clock gating technique is proposed with the latch-based design for reducing the dynamic and clock power consumption. The number of adder's circuit in both ALU and FIR circuits is less since it improves the overall efficiency of the system.
Thus, the proposed methodology concluded that the design and analysis of ALU based FIR filter for medical image processing give the efficient result on the way of achieving the factors such as power (Static & Dynamic), Delay (Path delay) area utilization, MSE and PSNR. Here the image processing of FIR results to MSE and PSNR values, which obtained a better result than the existing VLSI based image processing works. The latch-based clock gating circuit is connected with the proposed circuit, based on the gated clock signal, it optimizes the gated circuit of the whole design since it also reduces the error and provides the efficient power report. This proposed VLSI model is simulated using Xilinx ISE 14.5 and Modelsim synthesizes it; here with the help of MATLAB, with the adaptation of the 2018a tool, the image filtering was done.
由于采用了最优的超大规模集成电路，因此主要目标是降低面积、延迟和功率因数。通过这些加法器和乘法器，可以独立地启用 DSP 中的主要操作。FIR 滤波器使用具有时钟再生比较器的 MAC 单元进行设计。
在超大规模集成电路行业中，低功耗、缩短时间和高效能设计是各种应用的首选。加法器和乘法器在 VLSI 电路设计中起着至关重要的作用。最近的电子行业为各种实时应用使用数字滤波器。这利用了有限脉冲响应 (FIR) 和无限脉冲响应 (IIR) 滤波器，这里 FIR 滤波器比 IIR 滤波器更稳定。这种 FIR 滤波器将脉冲信号转换为有限形式，主要用于 DSP 处理器以实现高速。在这两个 ALU 和 FIR 电路中，增加了加法器和乘法器块的使用，这会消耗大量的功率。
拟议的研究工作使用时钟门控技术来降低功耗。这里基于锁存器的时钟门控技术提供了有效的结果。基于异或的逻辑电路降低了设计复杂性并利用了较少的面积。进位保存累加器是用于加法的数字加法器。它提供了两组输出，即部分和进位输出。行波进位加法器使用全加法器电路进行操作。它在最后一位传播进位值。此外，CSA 和 RCA 的组合利用较少的面积、高速和提供更好的吞吐量。在乘法器块中，使用基于异或的逻辑的布斯乘法器算法。这里提出的 FIR 滤波器是为执行视网膜图像的图像处理而设计的。这个过程在医学领域提高了更好的可视化方法。
因此，提出了一种基于 ALU 的带有基于锁存器的时钟门控技术的 FIR 滤波器，并对其进行了各种参数的设计和分析。这里提出了改进的加法器和乘法器，以提高系统的效率。提出了改进的进位保存加法器，通过结合行波进位加法器逻辑来提高加法器的性能。使用加和移位方法设计了增强的布斯乘法器，以减少计算结果的阶段数。此过程应用于执行视网膜图像的图像处理。在 VLSI 环境中设计基于 ALU 的 FIR 滤波器结构后，将图像加载到 MATLAB 中作为.png 格式，然后将其转换为十六进制文件，从 Xilinx 读取该文件以执行滤波过程。然后将 'dataout' 转换为二进制文件以获得滤波过程的结果。增强的布斯乘法器通过减少计算结果的阶段数来减少延迟。这里提出了基于锁存器的设计的时钟门控技术，用于降低动态和时钟功耗。由于提高了系统的整体效率，因此在 ALU 和 FIR 电路中加法器的数量都较少。
因此，提出的方法得出结论，用于医学图像处理的基于 ALU 的 FIR 滤波器的设计和分析在实现功率（静态和动态）、延迟（路径延迟）、面积利用率、均方误差和峰值信噪比等因素方面给出了有效的结果。这里 FIR 结果的图像处理得到了均方误差和峰值信噪比的值，比现有的基于 VLSI 的图像处理工作获得了更好的结果。基于锁存器的时钟门控电路与提出的电路相连，根据门控时钟信号，它优化了整个设计的门控电路，因为它还减少了错误并提供了有效的功率报告。这个提出的 VLSI 模型使用 Xilinx ISE 14.5 和 Modelsim 进行模拟；在这里，借助于 MATLAB，使用 2018a 工具的适应，完成了图像滤波。
