Graduate School of Information Science and Technology, Hokkaido University , North 14 West 9, Sapporo 060-0814, Japan.
Research Center for Integrated Quantum Electronics (RCIQE), Hokkaido University , North 13 West 8, Sapporo 060-8628, Japan.
Nano Lett. 2015 Nov 11;15(11):7253-7. doi: 10.1021/acs.nanolett.5b02165. Epub 2015 Oct 22.
III-V compound semiconductor and Ge are promising channel materials for future low-power and high-performance integrated circuits. A heterogeneous integration of these materials on the same platform, however, raises serious problem owing to a huge mismatch of carrier mobility. We proposed direct integration of perfectly vertically aligned InAs nanowires on Ge as a method for new alternative integrated circuits and demonstrated a high-performance InAs nanowire-vertical surrounding-gate transistor. Virtually 100% yield of vertically aligned InAs nanowires was achieved by controlling the initial surface of Ge and high-quality InAs nanowires were obtained regardless of lattice mismatch (6.7%). The transistor performance showed significantly higher conductivity with good gate control compared to Si-based conventional field-effect transistors: the drain current was 0.65 mA/μm, and the transconductance was 2.2 mS/μm at drain-source voltage of 0.50 V. These demonstrations are a first step for building alternative integrated circuits using vertical III-V/multigate planar Ge FETs.
III-V 族化合物半导体和锗是未来低功耗、高性能集成电路有前途的沟道材料。然而，由于载流子迁移率的巨大不匹配，这些材料在同一平台上的异质集成带来了严重的问题。我们提出了在 Ge 上直接集成完美垂直排列的 InAs 纳米线作为新型替代集成电路的方法，并展示了高性能的 InAs 纳米线-垂直环绕栅晶体管。通过控制 Ge 的初始表面，实现了垂直排列 InAs 纳米线的几乎 100%的合格率，并且无论晶格失配（6.7%）如何，都获得了高质量的 InAs 纳米线。与基于 Si 的传统场效应晶体管相比，该晶体管具有更好的栅极控制和更高的导电性：在 0.50V 的漏源电压下，漏极电流为 0.65mA/μm，跨导为 2.2mS/μm。这些演示是使用垂直 III-V/多栅平面 GeFET 构建替代集成电路的第一步。
