Cai Ronggang, Jonas Alain M
Bio &Soft Matter, Institute of Condensed Matter and Nanosciences, Université catholique de Louvain, Croix du Sud 1/L7.04.02, B1348 Louvain-la-Neuve, Belgium.
Sci Rep. 2016 Feb 24;6:22116. doi: 10.1038/srep22116.
We study the local ferroelectric polarization and depolarization of poly(vinylidene fluoride-co-trifluoroethylene) (P(VDF-TrFE)) in p-type ferroelectric field-effect transistors (FeFETs). Piezoresponse force microscopy (PFM) is used to obtain local maps of the polarization on model metal-semiconductor-ferroelectric stacks, and on FeFETs stripped from their top-gate electrode; transfer curves are measured on complete FeFETs. The influence of the semiconductor layer thickness and of the polarity and amplitude of the poling voltage are investigated. In accumulation, the stable "on" state consists of a uniform upward-polarized ferroelectric layer, with compensation holes accumulating at the ferroelectric/semiconducting interface. In depletion, the stable "off" state consists of a depolarized region in the center of the transistor channel, surrounded by partially downward-polarized regions over the source and drain electrodes and neighboring regions. The partial depolarization of these regions is due to the incomplete screening of polarization charges by the charges of the remote electrodes. Therefore, thinner semiconducting layers provide higher downward polarizations, which result in a more depleted transistor channel and a higher charge injection barrier between the electrodes and the semiconductor, leading to lower threshold voltages and higher on/off current values at zero gate bias. Clues for optimization of the devices are finally provided.
我们研究了p型铁电场效应晶体管(FeFET)中聚(偏二氟乙烯-三氟乙烯共聚物)(P(VDF-TrFE))的局部铁电极化和去极化。压电力显微镜(PFM)用于获取模型金属-半导体-铁电堆栈以及从其顶栅电极剥离的FeFET上极化的局部图;在完整的FeFET上测量转移曲线。研究了半导体层厚度以及极化电压的极性和幅度的影响。在积累状态下,稳定的“开”状态由均匀向上极化的铁电层组成,补偿空穴在铁电/半导体界面处积累。在耗尽状态下,稳定的“关”状态由晶体管沟道中心的去极化区域组成,该区域被源极和漏极电极以及相邻区域上部分向下极化的区域包围。这些区域的部分去极化是由于远程电极的电荷对极化电荷的不完全屏蔽所致。因此,较薄的半导体层提供更高的向下极化,这导致晶体管沟道更耗尽,电极与半导体之间的电荷注入势垒更高,从而在零栅极偏置下导致更低的阈值电压和更高的开/关电流值。最后提供了器件优化的线索。