Reduction of interface traps between poly-Si and SiO layers through the dielectric recovery effect during delayed pulse bias stress.

We investigate the interface trap behavior between tunneling oxide and poly-Si channel layer post erase/write cycling with a delayed pulse by using deep level transient spectroscopy. For comparison of the defect states depending on the stress pulses, a Schottky and a metal-oxide semiconductor device were fabricated. A defect state at about E  -0.51 eV in the Schottky device was measured before the annealing process. Three-hole trap states with activation energies of E  +0.28 eV, E  +0.53 eV, and E  +0.76 eV appeared after the post-annealing process. The electron trap was about E  -0.15 eV after erase/write 3000 cycling was applied at ±10 V for 100 ms at 25 °C and 85 °C. These defect states may have an effect on the charge loss behavior of the electrons localized in the charge trap layer at the retention mode of three-dimensional non-volatile memory devices. Dramatically, after the endurance stress was applied with a delayed pulse of 300 cycling at 85 °C for 50.4 h, no interface traps of the deep level transient spectroscopy spectra appeared. Dielectric recovery can decrease the density of the interface trap and improve the retention properties. This may have been caused by the passivation effect on the dangling bond of the interface traps.