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亚纳米级AlO / TiO叠层的电容-电压特性:介电和界面电荷密度

Capacitance-voltage characteristics of sub-nanometric AlO / TiO laminates: dielectric and interface charge densities.

作者信息

Kahouli Abdelkader, Elbahri Marwa Ben, Lebedev Oleg, Lüders Ulrike

机构信息

CRISMAT UMR6508 CNRS-ENSICAEN-Normandie Université, Caen, France.

出版信息

J Phys Condens Matter. 2017 Jul 12;29(27):275301. doi: 10.1088/1361-648X/aa7237. Epub 2017 Jun 1.

DOI:10.1088/1361-648X/aa7237
PMID:28569244
Abstract

Advanced amorphous sub-nanometric laminates based on TiO and AlO were deposited by atomic layer deposition at low temperature. Low densities of 'slow' and 'fast' interface states are achieved with values of 3.96 · 10 cm and 4.85 · 10 eV cm, respectively, by using a 40 nm laminate constituted of 0.7 nm TiO and 0.8 nm AlO. The sub-nanometric laminate shows a low hysteresis width of 20 mV due to the low oxide charge density of about 3.72 · 10 cm. Interestingly, such properties are required for stable and reliable performance of MOS capacitors and transistor operation. Thus, decreasing the individual layer thickness to the sub-nanometric range and combining two dielectric materials with oppositely charged defects may play a major role in the electrical response, highly promising for the application in future micro and nano-electronics applications.

摘要

基于TiO和AlO的先进非晶亚纳米层压板通过低温原子层沉积法制备。通过使用由0.7nm TiO和0.8nm AlO组成的40nm层压板,分别获得了密度较低的“慢”和“快”界面态,其值分别为3.96·10 cm和4.85·10 eV cm。由于约3.72·10 cm的低氧化物电荷密度,亚纳米层压板显示出20mV的低滞后宽度。有趣的是,MOS电容器的稳定可靠性能和晶体管操作需要这些特性。因此,将单个层厚度减小到亚纳米范围并结合具有相反电荷缺陷的两种介电材料可能在电响应中起主要作用,这对于未来的微纳电子应用极具前景。

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