School of Electrical and Electronic Engineering, Yonsei University , Seoul 03722, Republic of Korea.
Lam Research Corporation , Fremont, California 94538, United States.
ACS Nano. 2017 Aug 22;11(8):7841-7847. doi: 10.1021/acsnano.7b01998. Epub 2017 Jul 25.
Semiconductor integrated circuit chip industries have been striving to introduce porous ultralow-k (ULK) dielectrics into the multilevel interconnection process in order to improve their chip operation speed by reducing capacitance along the signal path. To date, however, highly porous ULK dielectrics (porosity >40%, dielectric constant (k) <2.4) have not been successfully adopted in real devices because the porous nature causes many serious problems, including noncontinuous barrier deposition, penetration of the barrier metal, and reliability issues. Here, a method that allows porous ULK dielectrics to be successfully used with a multilevel interconnection scheme is presented. The surface of the porous ULK dielectric film (k = 2.0, porosity ∼47%) could be completely sealed by a thin (<2 nm) polymer deposited by a multistep initiated chemical vapor deposition (iCVD) process. Using the iCVD process, a thin pore-sealing layer was localized only to the surface of the porous ULK dielectric film, which could minimize the increase of k; the final effective k was less than 2.2, and the penetration of metal barrier precursors into the dielectric film was completely blocked. The pore-sealed ULK dielectric film also exhibited excellent long-term reliability comparable to a dense low-k dielectric film.
半导体集成电路芯片行业一直在努力将多孔超低介电常数（ULK）电介质引入多层互连工艺中，以通过降低信号路径中的电容来提高芯片的运行速度。然而，到目前为止，高多孔 ULK 电介质（孔隙率>40%，介电常数（k）<2.4）尚未在实际设备中成功采用，因为多孔性会导致许多严重的问题，包括不连续的阻挡层沉积、阻挡金属的渗透以及可靠性问题。在这里，提出了一种允许多孔 ULK 电介质与多层互连方案成功结合的方法。多孔 ULK 介电薄膜（k = 2.0，孔隙率∼47%）的表面可以通过多步引发化学气相沉积（iCVD）工艺沉积的薄（<2nm）聚合物完全密封。使用 iCVD 工艺，仅将薄的孔密封层局部化到多孔 ULK 介电膜的表面，这可以最小化 k 的增加；最终的有效 k 小于 2.2，并且金属阻挡层前体完全被阻挡在介电膜中。孔密封的 ULK 介电膜还表现出与致密低 k 介电膜相当的优异的长期可靠性。
