Department of Physics and Astronomy, University of Kansas , Lawrence, Kansas 66045, United States.
Department of Physics, Astronomy and Materials Science, Missouri State University , Springfield, Missouri 65897, United States.
ACS Appl Mater Interfaces. 2017 Oct 25;9(42):37468-37475. doi: 10.1021/acsami.7b12170. Epub 2017 Oct 16.
Electron tunneling through high-quality, atomically thin dielectric films can provide a critical enabling technology for future microelectronics, bringing enhanced quantum coherent transport, fast speed, small size, and high energy efficiency. A fundamental challenge is in controlling the interface between the dielectric and device electrodes. An interfacial layer (IL) will contain defects and introduce defects in the dielectric film grown atop, preventing electron tunneling through the formation of shorts. In this work, we present the first systematic investigation of the IL in AlO dielectric films of 1-6 Å's in thickness on an Al electrode. We integrated several advanced approaches: molecular dynamics to simulate IL formation, in situ high vacuum sputtering atomic layer deposition (ALD) to synthesize AlO on Al films, and in situ ultrahigh vacuum scanning tunneling spectroscopy to probe the electron tunneling through the AlO. The IL had a profound effect on electron tunneling. We observed a reduced tunnel barrier height and soft-type dielectric breakdown which indicate that defects are present in both the IL and in the AlO. The IL forms primarily due to exposure of the Al to trace O and/or HO during the pre-ALD heating step of fabrication. As the IL was systematically reduced, by controlling the pre-ALD sample heating, we observed an increase of the ALD AlO barrier height from 0.9 to 1.5 eV along with a transition from soft to hard dielectric breakdown. This work represents a key step toward the realization of high-quality, atomically thin dielectrics with electron tunneling for the next generation of microelectronics.
电子通过高质量、原子级薄介电薄膜的隧穿可以为未来微电子学提供关键的使能技术，带来增强的量子相干输运、高速、小尺寸和高能量效率。一个基本的挑战是控制介电层与器件电极之间的界面。界面层（IL）将包含缺陷，并在介电薄膜中引入缺陷，通过形成短路来阻止电子隧穿。在这项工作中，我们首次系统地研究了厚度为 1-6Å 的 AlO 介电薄膜在 Al 电极上的 IL。我们综合了几种先进的方法：分子动力学模拟 IL 的形成、原位高真空溅射原子层沉积（ALD）在 Al 薄膜上合成 AlO、以及原位超高真空扫描隧道谱来探测电子通过 AlO 的隧穿。IL 对电子隧穿有深远的影响。我们观察到隧穿势垒高度降低和软击穿型介电击穿，这表明 IL 和 AlO 中都存在缺陷。IL 的形成主要是由于在预 ALD 加热步骤中，Al 暴露于痕量的 O 和/或 HO。随着 IL 的系统减少，通过控制预 ALD 样品加热，我们观察到 ALD AlO 势垒高度从 0.9eV 增加到 1.5eV，同时从软击穿过渡到硬击穿。这项工作是实现下一代微电子学中具有电子隧穿的高质量、原子级薄介电材料的关键一步。
