D'Angelo Robert, Wood Richard, Lowry Nathan, Freifeld Geremy, Huang Haiyao, Salthouse Christopher D, Hollosi Brent, Muresan Matthew, Uy Wes, Tran Nhut, Chery Armand, Poppe Dorothy C, Sonkusale Sameer
Draper Laboratory, Cambridge, MA 02139, U.S.A., and Tufts University, Medford, MA 02155, U.S.A.
Draper Laboratory, Cambridge, MA 02139. U.S.A.
Neural Comput. 2018 Sep;30(9):2439-2471. doi: 10.1162/neco_a_01106. Epub 2018 Jun 27.
Computer vision algorithms are often limited in their application by the large amount of data that must be processed. Mammalian vision systems mitigate this high bandwidth requirement by prioritizing certain regions of the visual field with neural circuits that select the most salient regions. This work introduces a novel and computationally efficient visual saliency algorithm for performing this neuromorphic attention-based data reduction. The proposed algorithm has the added advantage that it is compatible with an analog CMOS design while still achieving comparable performance to existing state-of-the-art saliency algorithms. This compatibility allows for direct integration with the analog-to-digital conversion circuitry present in CMOS image sensors. This integration leads to power savings in the converter by quantizing only the salient pixels. Further system-level power savings are gained by reducing the amount of data that must be transmitted and processed in the digital domain. The analog CMOS compatible formulation relies on a pulse width (i.e., time mode) encoding of the pixel data that is compatible with pulse-mode imagers and slope based converters often used in imager designs. This letter begins by discussing this time-mode encoding for implementing neuromorphic architectures. Next, the proposed algorithm is derived. Hardware-oriented optimizations and modifications to this algorithm are proposed and discussed. Next, a metric for quantifying saliency accuracy is proposed, and simulation results of this metric are presented. Finally, an analog synthesis approach for a time-mode architecture is outlined, and postsynthesis transistor-level simulations that demonstrate functionality of an implementation in a modern CMOS process are discussed.
计算机视觉算法的应用常常受到必须处理的大量数据的限制。哺乳动物视觉系统通过利用神经回路优先处理视野中的某些区域来减轻这种高带宽需求，这些神经回路会选择最显著的区域。这项工作引入了一种新颖且计算高效的视觉显著性算法，用于执行这种基于神经形态注意力的数据缩减。所提出的算法具有额外的优势，即它与模拟CMOS设计兼容，同时仍能实现与现有最先进的显著性算法相当的性能。这种兼容性允许与CMOS图像传感器中存在的模数转换电路直接集成。通过仅对显著像素进行量化，这种集成在转换器中实现了功耗节省。通过减少数字域中必须传输和处理的数据量，进一步实现了系统级的功耗节省。模拟CMOS兼容公式依赖于像素数据的脉冲宽度（即时域模式）编码，该编码与成像器设计中常用的脉冲模式成像器和基于斜率的转换器兼容。本文首先讨论用于实现神经形态架构的这种时域模式编码。接下来，推导所提出的算法。提出并讨论了针对该算法的面向硬件的优化和修改。接着，提出了一种用于量化显著性准确性的指标，并给出了该指标的仿真结果。最后，概述了一种用于时域模式架构的模拟合成方法，并讨论了在现代CMOS工艺中展示实现功能的合成后晶体管级仿真。
