Shin Ho Hyun, Chung Eui-Young
Samsung Electronics Company, Ltd., Hwasung 18448, Korea.
School of Electrical and Electronic Engineering, Yonsei University, Seoul 03722, Korea.
Micromachines (Basel). 2019 Feb 14;10(2):124. doi: 10.3390/mi10020124.
Recently, 3D-stacked dynamic random access memory (DRAM) has become a promising solution for ultra-high capacity and high-bandwidth memory implementations. However, it also suffers from memory wall problems due to long latency, such as with typical 2D-DRAMs. Although there are various cache management techniques and latency hiding schemes to reduce DRAM access time, in a high-performance system using high-capacity 3D-stacked DRAM, it is ultimately essential to reduce the latency of the DRAM itself. To solve this problem, various asymmetric in-DRAM cache structures have recently been proposed, which are more attractive for high-capacity DRAMs because they can be implemented at a lower cost in 3D-stacked DRAMs. However, most research mainly focuses on the architecture of the in-DRAM cache itself and does not pay much attention to proper management methods. In this paper, we propose two new management algorithms for the in-DRAM caches to achieve a low-latency and low-power 3D-stacked DRAM device. Through the computing system simulation, we demonstrate the improvement of energy delay product up to 67%.
最近，3D堆叠动态随机存取存储器（DRAM）已成为实现超高容量和高带宽存储器的一种很有前景的解决方案。然而，与典型的2D-DRAM一样，由于延迟长，它也存在内存墙问题。尽管有各种缓存管理技术和延迟隐藏方案来减少DRAM访问时间，但在使用高容量3D堆叠DRAM的高性能系统中，最终降低DRAM本身的延迟至关重要。为了解决这个问题，最近提出了各种非对称片内DRAM缓存结构，对于高容量DRAM来说，这些结构更具吸引力，因为它们可以在3D堆叠DRAM中以更低的成本实现。然而，大多数研究主要集中在片内DRAM缓存本身的架构上，而没有过多关注适当的管理方法。在本文中，我们提出了两种用于片内DRAM缓存的新管理算法，以实现低延迟、低功耗的3D堆叠DRAM器件。通过计算系统仿真，我们证明了能量延迟积提高了67%。
