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硅和多晶硅1T-DRAM的传感裕度分析

Analysis of the Sensing Margin of Silicon and Poly-Si 1T-DRAM.

作者信息

Kim Hyeonjeong, Yoo Songyi, Kang In-Man, Cho Seongjae, Sun Wookyung, Shin Hyungsoon

机构信息

Department of Electronic and Electrical Engineering, Ewha Womans University, Seoul 03760, Korea.

School of Electronics Engineering, Kyungpook National University, Daegu 702-701, Korea.

出版信息

Micromachines (Basel). 2020 Feb 23;11(2):228. doi: 10.3390/mi11020228.

Abstract

Recently, one-transistor dynamic random-access memory (1T-DRAM) cells having a polysilicon body (poly-Si 1T-DRAM) have attracted attention as candidates to replace conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). Poly-Si 1T-DRAM enables the cost-effective implementation of a silicon-on-insulator (SOI) structure and a three-dimensional (3D) stacked architecture for increasing integration density. However, studies on the transient characteristics of poly-Si 1T-DRAM are still lacking. In this paper, with TCAD simulation, we examine the differences between the memory mechanisms in poly-Si and silicon body 1T-DRAM. A silicon 1T-DRAM cell's data state is determined by the number of holes stored in a floating body (FB), while a poly-Si 1T-DRAM cell's state depends on the number of electrons trapped in its grain boundary (GB). This means that a poly-Si 1T-DRAM can perform memory operations by using GB as a storage region in thin body devices with a small FB area.

摘要

最近,具有多晶硅体的单晶体管动态随机存取存储器(1T-DRAM)单元(多晶硅1T-DRAM)作为取代传统单晶体管单电容器动态随机存取存储器(1T-1C DRAM)的候选者受到了关注。多晶硅1T-DRAM能够以具有成本效益的方式实现绝缘体上硅(SOI)结构和三维(3D)堆叠架构,以提高集成密度。然而,关于多晶硅1T-DRAM瞬态特性的研究仍然不足。在本文中,通过TCAD模拟,我们研究了多晶硅和硅体1T-DRAM中存储机制的差异。硅1T-DRAM单元的数据状态由存储在浮体(FB)中的空穴数量决定,而多晶硅1T-DRAM单元的状态则取决于捕获在其晶界(GB)中的电子数量。这意味着多晶硅1T-DRAM可以通过将GB用作具有小FB区域的薄体器件中的存储区域来执行存储操作。

https://cdn.ncbi.nlm.nih.gov/pmc/blobs/76cb/7074760/10ee655df104/micromachines-11-00228-g001.jpg

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