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硅和多晶硅1T-DRAM的传感裕度分析

Analysis of the Sensing Margin of Silicon and Poly-Si 1T-DRAM.

作者信息

Kim Hyeonjeong, Yoo Songyi, Kang In-Man, Cho Seongjae, Sun Wookyung, Shin Hyungsoon

机构信息

Department of Electronic and Electrical Engineering, Ewha Womans University, Seoul 03760, Korea.

School of Electronics Engineering, Kyungpook National University, Daegu 702-701, Korea.

出版信息

Micromachines (Basel). 2020 Feb 23;11(2):228. doi: 10.3390/mi11020228.

DOI:10.3390/mi11020228
PMID:32102235
原文链接:https://pmc.ncbi.nlm.nih.gov/articles/PMC7074760/
Abstract

Recently, one-transistor dynamic random-access memory (1T-DRAM) cells having a polysilicon body (poly-Si 1T-DRAM) have attracted attention as candidates to replace conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). Poly-Si 1T-DRAM enables the cost-effective implementation of a silicon-on-insulator (SOI) structure and a three-dimensional (3D) stacked architecture for increasing integration density. However, studies on the transient characteristics of poly-Si 1T-DRAM are still lacking. In this paper, with TCAD simulation, we examine the differences between the memory mechanisms in poly-Si and silicon body 1T-DRAM. A silicon 1T-DRAM cell's data state is determined by the number of holes stored in a floating body (FB), while a poly-Si 1T-DRAM cell's state depends on the number of electrons trapped in its grain boundary (GB). This means that a poly-Si 1T-DRAM can perform memory operations by using GB as a storage region in thin body devices with a small FB area.

摘要

最近,具有多晶硅体的单晶体管动态随机存取存储器(1T-DRAM)单元(多晶硅1T-DRAM)作为取代传统单晶体管单电容器动态随机存取存储器(1T-1C DRAM)的候选者受到了关注。多晶硅1T-DRAM能够以具有成本效益的方式实现绝缘体上硅(SOI)结构和三维(3D)堆叠架构,以提高集成密度。然而,关于多晶硅1T-DRAM瞬态特性的研究仍然不足。在本文中,通过TCAD模拟,我们研究了多晶硅和硅体1T-DRAM中存储机制的差异。硅1T-DRAM单元的数据状态由存储在浮体(FB)中的空穴数量决定,而多晶硅1T-DRAM单元的状态则取决于捕获在其晶界(GB)中的电子数量。这意味着多晶硅1T-DRAM可以通过将GB用作具有小FB区域的薄体器件中的存储区域来执行存储操作。

https://cdn.ncbi.nlm.nih.gov/pmc/blobs/76cb/7074760/f0f4f4281e3a/micromachines-11-00228-g006.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/76cb/7074760/10ee655df104/micromachines-11-00228-g001.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/76cb/7074760/635fdc6848c4/micromachines-11-00228-g002.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/76cb/7074760/a555e6838cc8/micromachines-11-00228-g003.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/76cb/7074760/092dd62b234a/micromachines-11-00228-g004.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/76cb/7074760/4976d991cc34/micromachines-11-00228-g005.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/76cb/7074760/f0f4f4281e3a/micromachines-11-00228-g006.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/76cb/7074760/10ee655df104/micromachines-11-00228-g001.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/76cb/7074760/635fdc6848c4/micromachines-11-00228-g002.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/76cb/7074760/a555e6838cc8/micromachines-11-00228-g003.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/76cb/7074760/092dd62b234a/micromachines-11-00228-g004.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/76cb/7074760/4976d991cc34/micromachines-11-00228-g005.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/76cb/7074760/f0f4f4281e3a/micromachines-11-00228-g006.jpg

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Special Issue on Miniaturized Transistors, Volume II.

本文引用的文献

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An Analysis of Hole Trapping at Grain Boundary or Poly-Si Floating-Body MOSFET.
J Nanosci Nanotechnol. 2018 Sep 1;18(9):6584-6587. doi: 10.1166/jnn.2018.15702.
2
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J Nanosci Nanotechnol. 2011 Jul;11(7):5608-11. doi: 10.1166/jnn.2011.4334.
《微型晶体管特刊第二卷》
Micromachines (Basel). 2022 Apr 12;13(4):603. doi: 10.3390/mi13040603.
4
Circuit Optimization Method to Reduce Disturbances in Poly-Si 1T-DRAM.降低多晶硅1T-DRAM中干扰的电路优化方法
Micromachines (Basel). 2021 Oct 2;12(10):1209. doi: 10.3390/mi12101209.
5
Analysis of a Lateral Grain Boundary for Reducing Performance Variations in Poly-Si 1T-DRAM.用于减少多晶硅1T-DRAM性能变化的横向晶界分析
Micromachines (Basel). 2020 Oct 22;11(11):952. doi: 10.3390/mi11110952.