Gu Hwa Young, Kim Sangwan
Department of Electrical and Computer Engineering, Ajou University, Suwon 16499, Korea.
Micromachines (Basel). 2019 Mar 30;10(4):229. doi: 10.3390/mi10040229.
Recently, tunnel field-effect transistors (TFETs) have been regarded as next-generation ultra-low-power semi-conductor devices. To commercialize the TFETs, however, it is necessary to improve an on-state current caused by tunnel-junction resistance and to suppress a leakage current from ambipolar current (). In this paper, we suggest a novel TFET which features double gate, vertical, and trapezoid isosceles channel structure to solve the above-mentioned technical issues. The device design is optimized by examining its electrical characteristics with the help of technology computer-aided design (TCAD) simulation. As a result, double-gate isosceles trapezoid (DGIT) TFET shows a much better performance than the conventional TFET in terms of ON-state current (), , and gate-to-drain capacitance (). It is confirmed that an inverter composed of DGIT-TFETs can operate with less than 1 ns intrinsic delay time and negligible voltage overshoot.
最近，隧穿场效应晶体管（TFET）被视为下一代超低功耗半导体器件。然而，为了使TFET商业化，有必要提高由隧道结电阻引起的导通电流，并抑制来自双极性电流的漏电流。在本文中，我们提出了一种新颖的TFET，其具有双栅、垂直和梯形等腰沟道结构，以解决上述技术问题。借助技术计算机辅助设计（TCAD）模拟来检查其电气特性，从而对器件设计进行优化。结果表明，双栅等腰梯形（DGIT）TFET在导通电流、亚阈值摆幅和栅漏电容方面比传统TFET表现出更好的性能。证实了由DGIT-TFET组成的反相器能够以小于1 ns的固有延迟时间和可忽略的电压过冲运行。
