IEEE Trans Biomed Circuits Syst. 2020 Apr;14(2):297-304. doi: 10.1109/TBCAS.2019.2959412. Epub 2019 Dec 12.
A multi-channel biopotential recording analog front-end (AFE) with a fully integrated area-efficient driven-right-leg (DRL) circuit is presented in this paper. The proposed AFE includes 10 channels of low-noise capacitive coupled instrumentation amplifier (CCIA), one shared 10-bit SAR ADC and a fully integrated DRL to enhance the system-level common-mode rejection ratio (CMRR). The proposed DRL circuit senses the common-mode at the CCIA output so that the AFE gain is reused as the DRL loop gain. Therefore, area efficient unit-gain buffer with small averaging capacitors can be used in DRL circuit to reduce the circuit area significantly. The proposed AFE has been implemented in a standard 0.18-μm CMOS process. The DRL circuit achieved more than 85% chip area reduction compared to the state-of-art on-chip DRL circuits and maximum 60 dB enhancement to system-level CMRR. Measurement results show high/low AFE gain of 60 dB/54 dB respectively with 1 μA/channel current consumption under 1.0 V power supply. The measured AFE input-referred noise in 1 Hz - 10k Hz range is 4.2 μV and the maximum system-level CMRR is 110 dB.
本文提出了一种具有完全集成的高效率驱动右腿（DRL）电路的多通道生物电位记录模拟前端（AFE）。所提出的 AFE 包括 10 个通道的低噪声电容耦合仪表放大器（CCIA）、一个共享的 10 位 SAR ADC 和一个完全集成的 DRL，以提高系统级共模抑制比（CMRR）。所提出的 DRL 电路在 CCIA 输出处感测共模，因此 AFE 增益被重新用作 DRL 环路增益。因此，可以在 DRL 电路中使用面积效率高的单位增益缓冲器和小平均电容器，从而显著减小电路面积。该 AFE 已在标准的 0.18-μm CMOS 工艺中实现。与最先进的片上 DRL 电路相比，DRL 电路的面积减少了 85%以上，系统级 CMRR 最大提高了 60dB。测量结果表明，在 1.0 V 电源下，高/低 AFE 增益分别为 60 dB/54 dB，每个通道的电流消耗为 1 μA。在 1 Hz - 10k Hz 范围内测量到的 AFE 输入参考噪声为 4.2 μV，最大系统级 CMRR 为 110 dB。
