• 文献检索
  • 文档翻译
  • 深度研究
  • 学术资讯
  • Suppr Zotero 插件Zotero 插件
  • 邀请有礼
  • 套餐&价格
  • 历史记录
应用&插件
Suppr Zotero 插件Zotero 插件浏览器插件Mac 客户端Windows 客户端微信小程序
定价
高级版会员购买积分包购买API积分包
服务
文献检索文档翻译深度研究API 文档MCP 服务
关于我们
关于 Suppr公司介绍联系我们用户协议隐私条款
关注我们

Suppr 超能文献

核心技术专利:CN118964589B侵权必究
粤ICP备2023148730 号-1Suppr @ 2026

文献检索

告别复杂PubMed语法,用中文像聊天一样搜索,搜遍4000万医学文献。AI智能推荐,让科研检索更轻松。

立即免费搜索

文件翻译

保留排版,准确专业,支持PDF/Word/PPT等文件格式,支持 12+语言互译。

免费翻译文档

深度研究

AI帮你快速写综述,25分钟生成高质量综述,智能提取关键信息,辅助科研写作。

立即免费体验

Bottom-Up Masking of Si/Ge Surfaces and Nanowire Heterostructures Surface-Initiated Polymerization and Selective Etching.

作者信息

Mohabir Amar T, Tutuncuoglu Gozde, Weiss Trent, Vogel Eric M, Filler Michael A

机构信息

School of Chemical & Biomolecular Engineering , Georgia Institute of Technology , Atlanta , Georgia 30332 , United States.

School of Materials Science & Engineering , Georgia Institute of Technology , Atlanta , Georgia 30332 , United States.

出版信息

ACS Nano. 2020 Jan 28;14(1):282-288. doi: 10.1021/acsnano.9b04363. Epub 2019 Dec 26.

DOI:10.1021/acsnano.9b04363
PMID:31854980
Abstract

The fully bottom-up and scalable synthesis of complex micro/nanoscale materials and functional devices requires masking methods to define key features and direct the deposition of various coatings and films. Here, we demonstrate selective coaxial lithography etching of surfaces (SCALES), an enabling bottom-up process to add polymer masks to micro/nanoscale objects. SCALES is a three-step process, including (1) bottom-up synthesis of compositionally modulated structures, (2) surface-initiated polymerization of a conformal mask, and (3) selective removal of the mask only from regions whose underlying surface is susceptible to an etchant. We demonstrate the key features of and characterize the SCALES process with a series of model Si/Ge systems: Si and Ge wafers, Si and Ge nanowires, and Si/Ge heterostructure nanowires.

摘要

相似文献

1
Bottom-Up Masking of Si/Ge Surfaces and Nanowire Heterostructures Surface-Initiated Polymerization and Selective Etching.
ACS Nano. 2020 Jan 28;14(1):282-288. doi: 10.1021/acsnano.9b04363. Epub 2019 Dec 26.
2
Bottom-up nanoscale patterning and selective deposition on silicon nanowires.硅纳米线上的自下而上纳米级图案化与选择性沉积
Nanotechnology. 2021 Dec 13;33(10). doi: 10.1088/1361-6528/ac3bed.
3
Strain-induced structural defects and their effects on the electrochemical performances of silicon core/germanium shell nanowire heterostructures.应变诱导的结构缺陷及其对硅核/锗壳纳米线异质结构电化学性能的影响。
Nanoscale. 2017 Jan 19;9(3):1213-1220. doi: 10.1039/c6nr07681e.
4
Degradation of Si/Ge core/shell nanowire heterostructures during lithiation and delithiation at 0.8 and 20 A g.在 0.8 和 20 A g 下进行锂化和脱锂过程中 Si/Ge 核/壳纳米线异质结构的降解
Nanoscale. 2018 Apr 26;10(16):7343-7351. doi: 10.1039/c8nr00865e.
5
Monolithic Axial and Radial Metal-Semiconductor Nanowire Heterostructures.整体轴向和径向金属-半导体纳米线异质结构
Nano Lett. 2018 Dec 12;18(12):7692-7697. doi: 10.1021/acs.nanolett.8b03366. Epub 2018 Nov 20.
6
Fabrication of Coaxial Si(1-x)Ge(x) Heterostructure Nanowires by O(2) Flow-Induced Bifurcate Reactions.通过O(2)流诱导的分叉反应制备同轴Si(1-x)Ge(x)异质结构纳米线
Nanoscale Res Lett. 2010 Jun 17;5(10):1535-1539. doi: 10.1007/s11671-010-9673-3.
7
Versatile Fabrication of Self-Aligned Nanoscale Hall Devices Using Nanowire Masks.使用纳米线掩模实现自对准纳米级霍尔器件的多功能制造
Nano Lett. 2016 May 11;16(5):3109-15. doi: 10.1021/acs.nanolett.6b00398. Epub 2016 Apr 8.
8
Electrochemical Deposition of Conformal and Functional Layers on High Aspect Ratio Silicon Micro/Nanowires.在高纵横比硅微/纳线上进行保形和功能层的电化学沉积。
Nano Lett. 2017 Jul 12;17(7):4502-4507. doi: 10.1021/acs.nanolett.7b01950. Epub 2017 Jun 23.
9
Erratum: Preparation of Poly(pentafluorophenyl acrylate) Functionalized SiO2 Beads for Protein Purification.勘误:用于蛋白质纯化的聚(丙烯酸五氟苯酯)功能化二氧化硅微珠的制备
J Vis Exp. 2019 Apr 30(146). doi: 10.3791/6328.
10
A general lithography-free method of microscale/nanoscale fabrication and patterning on Si and Ge surfaces.一种在硅和锗表面进行微尺度/纳米尺度制造和图案化的通用无光刻方法。
Nanoscale Res Lett. 2012 Feb 8;7(1):110. doi: 10.1186/1556-276X-7-110.