Borejko Tomasz, Marcinek Krzysztof, Siwiec Krzysztof, Narczyk Paweł, Borkowski Adam, Butryn Igor, Łuczyk Arkadiusz, Pietroń Daniel, Plasota Maciej, Reszewicz Szymon, Wiechowski Łukasz, Pleskacz Witold A
Warsaw University of Technology, Institute of Microelectronics and Optoelectronics, ul. Koszykowa 75, 00-662 Warsaw, Poland.
ChipCraft Sp. z o.o., ul. Dobrzańskiego 3 lok. BS073, 20-262 Lublin, Poland.
Sensors (Basel). 2020 Feb 16;20(4):1069. doi: 10.3390/s20041069.
A dual-frequency all-in-one Global Navigation Satellite System (GNSS) receiver with a multi-core 32-bit RISC (reduced instruction set computing) application processor was integrated and manufactured as a System-on-Chip (SoC) in a 110 nm CMOS (complementary metal-oxide semiconductor) process. The GNSS RF (radio frequency) front-end with baseband navigation engine is able to receive, simultaneously, Galileo (European Global Satellite Navigation System) E1/E5ab, GPS (US Global Positioning System) L1/L1C/L5, BeiDou (Chinese Navigation Satellite System) B1/B2, GLONASS (GLObal NAvigation Satellite System of Russian Government) L1/L3/L5, QZSS (Quasi-Zenith Satellite System development by the Japanese government) L1/L5 and IRNSS (Indian Regional Navigation Satellite System) L5, as well as all SBAS (Satellite Based Augmentation System) signals. The ability of the GNSS to detect such a broad range of signals allows for high-accuracy positioning. The whole SoC (system-on-chip), which is connected to a small passive antenna, provides precise position, velocity and time or raw GNSS data for hybridization with the IMU (inertial measurement unit) without the need for an external application processor. Additionally, user application can be executed directly in the SoC. It works in the -40 to +105 °C temperature range with a 1.5 V supply. The assembled test-chip takes 100 pins in a QFN (quad-flat no-leads) package and needs only a quartz crystal for the on-chip reference clock driver and optional SAW (surface acoustic wave) filters. The radio performance for both wideband (52 MHz) channels centered at L1/E1 and L5/E5 is NF = 2.3 dB, G = 131 dB, with 121 dBc/Hz of phase noise @ 1 MHz offset from the carrier, consumes 35 mW and occupies a 4.5 mm silicon area. The SoC reported in the paper is the first ever dual-frequency single-chip GNSS receiver equipped with a multi-core application microcontroller integrated with embedded flash memory for the user application program.
一款集成了多核32位RISC（精简指令集计算）应用处理器的双频一体化全球导航卫星系统（GNSS）接收器，采用110纳米互补金属氧化物半导体（CMOS）工艺制造为片上系统（SoC）。带有基带导航引擎的GNSS射频（RF）前端能够同时接收伽利略（欧洲全球卫星导航系统）E1/E5ab、GPS（美国全球定位系统）L1/L1C/L5、北斗（中国导航卫星系统）B1/B2、格洛纳斯（俄罗斯政府的全球导航卫星系统）L1/L3/L5、准天顶卫星系统（日本政府开发的）L1/L5以及印度区域导航卫星系统（IRNSS）L5，以及所有卫星增强系统（SBAS）信号。GNSS检测如此广泛信号的能力实现了高精度定位。整个SoC（片上系统）连接到一个小型无源天线，可提供精确的位置、速度和时间，或原始GNSS数据用于与惯性测量单元（IMU）进行融合，无需外部应用处理器。此外，用户应用程序可直接在SoC中执行。它在-40至+105°C的温度范围内工作，电源电压为1.5V。组装后的测试芯片采用四方扁平无引脚（QFN）封装，有100个引脚，仅需一个石英晶体用于片上参考时钟驱动器和可选的表面声波（SAW）滤波器。以L1/E1和L5/E5为中心的两个宽带（52MHz）通道的射频性能为：噪声系数NF = 2.3dB，增益G = 131dB，在偏离载波1MHz处的相位噪声为121dBc/Hz，功耗为35mW，占用4.5平方毫米的硅面积。本文报道的SoC是首款配备多核应用微控制器且集成了用于用户应用程序的嵌入式闪存的双频单芯片GNSS接收器。
