Bilmes Alexander, Megrant Anthony, Klimov Paul, Weiss Georg, Martinis John M, Ustinov Alexey V, Lisenfeld Jürgen
Physikalisches Institut, Karlsruhe Institute of Technology, Karlsruhe, 76131, Germany.
Google, Santa Barbara, California, 93117, USA.
Sci Rep. 2020 Feb 20;10(1):3090. doi: 10.1038/s41598-020-59749-y.
Solid-state quantum coherent devices are quickly progressing. Superconducting circuits, for instance, have already been used to demonstrate prototype quantum processors comprising a few tens of quantum bits. This development also revealed that a major part of decoherence and energy loss in such devices originates from a bath of parasitic material defects. However, neither the microscopic structure of defects nor the mechanisms by which they emerge during sample fabrication are understood. Here, we present a technique to obtain information on locations of defects relative to the thin film edge of the qubit circuit. Resonance frequencies of defects are tuned by exposing the qubit sample to electric fields generated by electrodes surrounding the chip. By determining the defect's coupling strength to each electrode and comparing it to a simulation of the field distribution, we obtain the probability at which location and at which interface the defect resides. This method is applicable to already existing samples of various qubit types, without further on-chip design changes. It provides a valuable tool for improving the material quality and nano-fabrication procedures towards more coherent quantum circuits.
固态量子相干器件正在迅速发展。例如，超导电路已被用于展示由几十个量子比特组成的量子处理器原型。这一发展还表明，此类器件中退相干和能量损失的主要部分源于寄生材料缺陷的“库”。然而，缺陷的微观结构及其在样品制造过程中出现的机制都尚不明确。在此，我们提出一种技术，用于获取关于缺陷相对于量子比特电路薄膜边缘位置的信息。通过将量子比特样品暴露于芯片周围电极产生的电场中，来调节缺陷的共振频率。通过确定缺陷与每个电极的耦合强度，并将其与场分布模拟结果进行比较，我们可以得出缺陷所在的位置以及界面的概率。该方法适用于各种量子比特类型的现有样品，无需对芯片进行进一步设计更改。它为提高材料质量和纳米制造工艺以实现更相干的量子电路提供了一个有价值的工具。
