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用于减少多晶硅1T-DRAM性能变化的横向晶界分析

Analysis of a Lateral Grain Boundary for Reducing Performance Variations in Poly-Si 1T-DRAM.

作者信息

Yoo Songyi, Sun Wookyung, Shin Hyungsoon

机构信息

Department of Electronic and Electrical Engineering, Ewha Womans University, Seoul 03760, Korea.

Smart Factory Multidisciplinary Program, Ewha Womans University, Seoul 03760, Korea.

出版信息

Micromachines (Basel). 2020 Oct 22;11(11):952. doi: 10.3390/mi11110952.

DOI:10.3390/mi11110952
PMID:33105643
原文链接:https://pmc.ncbi.nlm.nih.gov/articles/PMC7690446/
Abstract

A capacitorless one-transistor dynamic random-access memory device that uses a poly-silicon body (poly-Si 1T-DRAM) has been suggested to overcome the scaling limit of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). A poly-Si 1T-DRAM cell operates as a memory by utilizing the charge trapped at the grain boundaries (GBs) of its poly-Si body; vertical GBs are formed randomly during fabrication. This paper describes technology computer aided design (TCAD) device simulations performed to investigate the sensing margin and retention time of poly-Si 1T-DRAM as a function of its lateral GB location. The results show that the memory's operating mechanism changes with the GB's lateral location because of a corresponding change in the number of trapped electrons or holes. We determined the optimum lateral GB location for the best memory performance by considering both the sensing margin and retention time. We also performed simulations to analyze the effect of a lateral GB on the operation of a poly-Si 1T-DRAM that has a vertical GB. The memory performance of devices without a lateral GB significantly deteriorates when a vertical GB is located near the source or drain junction, while devices with a lateral GB have little change in memory characteristics with different vertical GB locations. This means that poly-Si 1T-DRAM devices with a lateral GB can operate reliably without any memory performance degradation from randomly determined vertical GB locations.

摘要

一种无电容器的单晶体管动态随机存取存储器器件(多晶硅体单晶体管动态随机存取存储器,即poly-Si 1T-DRAM)已被提出,以克服传统的单晶体管单电容器动态随机存取存储器(1T-1C DRAM)的缩放限制。多晶硅体单晶体管动态随机存取存储器单元通过利用捕获在其多晶硅体晶界(GBs)处的电荷来作为存储器工作;垂直晶界在制造过程中随机形成。本文描述了为研究多晶硅体单晶体管动态随机存取存储器的传感裕度和保持时间作为其横向晶界位置的函数而进行的技术计算机辅助设计(TCAD)器件模拟。结果表明,由于捕获的电子或空穴数量的相应变化,存储器的工作机制随晶界的横向位置而变化。通过同时考虑传感裕度和保持时间,我们确定了实现最佳存储器性能的最佳横向晶界位置。我们还进行了模拟,以分析横向晶界对具有垂直晶界的多晶硅体单晶体管动态随机存取存储器操作的影响。当垂直晶界位于源极或漏极结附近时,没有横向晶界的器件的存储器性能会显著恶化,而具有横向晶界的器件在不同垂直晶界位置时存储器特性变化很小。这意味着具有横向晶界的多晶硅体单晶体管动态随机存取存储器器件可以可靠地运行,而不会因随机确定的垂直晶界位置而导致任何存储器性能下降。

https://cdn.ncbi.nlm.nih.gov/pmc/blobs/b6fd/7690446/193ca526eefa/micromachines-11-00952-g012.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/b6fd/7690446/4cf832531587/micromachines-11-00952-g009.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/b6fd/7690446/34cffe534547/micromachines-11-00952-g010.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/b6fd/7690446/c242a11abd4e/micromachines-11-00952-g011.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/b6fd/7690446/193ca526eefa/micromachines-11-00952-g012.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/b6fd/7690446/4cf832531587/micromachines-11-00952-g009.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/b6fd/7690446/34cffe534547/micromachines-11-00952-g010.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/b6fd/7690446/c242a11abd4e/micromachines-11-00952-g011.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/b6fd/7690446/193ca526eefa/micromachines-11-00952-g012.jpg

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本文引用的文献

1
Analysis of the Sensing Margin of Silicon and Poly-Si 1T-DRAM.硅和多晶硅1T-DRAM的传感裕度分析
Micromachines (Basel). 2020 Feb 23;11(2):228. doi: 10.3390/mi11020228.
2
Capacitorless 1T-DRAM on crystallized poly-Si TFT.基于非晶硅薄膜晶体管的无电容1T-DRAM。
J Nanosci Nanotechnol. 2011 Jul;11(7):5608-11. doi: 10.1166/jnn.2011.4334.