Department of Electronic and Electrical Engineering, Ewha Womans University, Seoul 03760, Korea.
School of Electronics Engineering, Kyungpook National University, Daegu 702-701, Korea.
J Nanosci Nanotechnol. 2021 Aug 1;21(8):4216-4222. doi: 10.1166/jnn.2021.19389.
A capacitorless one-transistor dynamic random-access memory cell with a polysilicon body (poly-Si 1T-DRAM) has a cost-effective fabrication process and allows a three-dimensional stacked architecture that increases the integration density of memory cells. Also, since this device uses grain boundaries (GBs) as a storage region, it can be operated as a memory cell even in a thin body device. GBs are important to the memory characteristics of poly-Si 1T-DRAM because the amount of trapped charge in the GBs determines the memory's data state. In this paper, we report on a statistical analysis of the memory characteristics of poly-Si 1T-DRAM cells according to the number and location of GBs using TCAD simulation. As the number of GBs increases, the sensing margin and retention time of memory cells deteriorate due to increasing trapped electron charge. Also, "0" state current increases and memory performance degrades in cells where all GBs are adjacent to the source or drain junction side in a strong electric field. These results mean that in poly-Si 1T-DRAM design, the number and location of GBs in a channel should be considered for optimal memory performance.
一种无电容器的单晶体管动态随机存取存储单元，具有多晶硅体 (poly-Si 1T-DRAM)，具有具有成本效益的制造工艺，并允许使用三维堆叠架构，从而增加存储单元的集成密度。此外，由于该器件将晶界 (GB) 用作存储区域，因此即使在薄体器件中也可以将其用作存储单元。晶界对多晶硅 1T-DRAM 的存储特性很重要，因为晶界中捕获的电荷量决定了存储的数据状态。在本文中，我们根据 TCAD 模拟中晶界的数量和位置，对多晶硅 1T-DRAM 单元的存储特性进行了统计分析。随着晶界数量的增加，由于捕获电子电荷的增加，存储单元的感测裕度和保持时间会恶化。此外，在所有晶界都靠近源极或漏极结侧的强电场中的单元中，“0”状态电流增加，存储性能下降。这些结果意味着在 poly-Si 1T-DRAM 设计中，应考虑沟道中晶界的数量和位置，以实现最佳的存储性能。
