Xiao Yao, Lu Zhifei, Ren Zhaofeng, Peng Xizhu, Tang He
School of Electronic Science and Engineering, SoC Design Center, University of Electronic Science and Technology of China, Chengdu, 610054, China.
Nanoscale Res Lett. 2020 Mar 6;15(1):58. doi: 10.1186/s11671-020-3284-4.
The bandwidth of a ΔΣ modulator is limited by the clock rate due to the oversampling ratio requirement. As the nanoscale CMOS processes are developing rapidly, it is possible to design wide bandwidth and high dynamic range continuous-time ΔΣ modulators for high-frequency applications. This paper proposes a 3rd-order 4-bit continuous-time ΔΣ modulator with a single-loop feedforward topology. This modulator is designed in a 40-nm CMOS process and achieves 80-dB dynamic range and a 100-MHz bandwidth at a clock rate of 2.4 GHz. The modulator consumes 69.7 mW from 1.2 V power supply.
由于过采样率要求，ΔΣ调制器的带宽受时钟速率限制。随着纳米级CMOS工艺的迅速发展，有可能为高频应用设计宽带宽和高动态范围的连续时间ΔΣ调制器。本文提出了一种具有单环前馈拓扑结构的三阶4位连续时间ΔΣ调制器。该调制器采用40纳米CMOS工艺设计，在2.4吉赫兹的时钟速率下实现了80分贝的动态范围和100兆赫兹的带宽。该调制器从1.2伏电源消耗69.7毫瓦的功率。
