Scalinx, 75013 Paris, France.
Telecom Paris, 91120 Palaiseau, France.
Sensors (Basel). 2022 Dec 20;23(1):36. doi: 10.3390/s23010036.
This paper describes a Delta Sigma ADC IC that embeds a 5th-order Continuous-Time Delta Sigma modulator with 40 MHz signal bandwidth, a low ripple 20 to 80 MS/s variable-rate digital decimation filter, a bandgap voltage reference, and high-speed CML buffers on a single die. The ADC also integrates on-chip calibrations for RC time-constant variation and quantizer offset. The chip was fabricated in a 1P7M 65 nm CMOS process. Clocked at 640 MHz, the Continuous-Time Delta Sigma modulator achieves 11-bit ENOB and 76.5 dBc THD up to 40 MHz of signal bandwidth while consuming 82.3 mW.
本文描述了一款 Delta Sigma ADC IC，该 IC 采用了 5 阶连续时间 Delta Sigma 调制器，具有 40MHz 的信号带宽、低纹波的 20 至 80MS/s 可变速率数字抽取滤波器、带隙电压基准和高速 CML 缓冲器，所有这些都集成在单个芯片上。该 ADC 还集成了片上校准功能，用于 RC 时间常数变化和量化器偏移。该芯片采用 1P7M 65nm CMOS 工艺制造。在 640MHz 时钟频率下，连续时间 Delta Sigma 调制器在 40MHz 的信号带宽下实现了 11 位 ENOB 和 76.5dBc THD，同时仅消耗 82.3mW 功率。
