Mun Hye Jin, Cho Min Su, Jung Jun Hyeok, Jang Won Douk, Lee Sang Ho, Jang Jaewon, Bae Jin-Hyuk, Kang In Man
School of Electronics Engineering, Kyungpook National University, Daegu 41566, Republic of Korea.
J Nanosci Nanotechnol. 2020 Nov 1;20(11):6616-6621. doi: 10.1166/jnn.2020.18769.
In this paper, we demonstrate the characteristics of a complementary metal-oxide-semiconductor (CMOS) logic inverter based on a polycrystalline-silicon (poly-Si) layer with a single grain boundary (GB). The proposed nanoscale CMOS logic inverter had been constructed on a poly-Si layer with a GB including four kind of traps at the center of the channel. The simulation variables are the acceptor-like deep trap (ADT), the donor-like deep trap (DDT), the acceptor-like shallow trap (AST) and the donor-like shallow trap (DST). The ADT and the DDT much stronger influences on the DC characteristics of the devices than the AST and the DST. The variation of voltage-transfer-curve (VTC) for CMOS devices directly affected the CMOS logic inverter with different traps.
