Lee Sang Ho, Cho Min Su, Jung Jun Hyeok, Jang Won Douk, Mun Hye Jin, Jang Jaewon, Bae Jin-Hyuk, Kang In Man
School of Electronics Engineering, Kyungpook National University Daegu 41566, Republic of Korea.
J Nanosci Nanotechnol. 2020 Nov 1;20(11):6632-6637. doi: 10.1166/jnn.2020.18768.
In this paper, we adopt the vertical core-shell nanowire field-effect transistors based on the Silicon-germanium (SiGe)/strained-silicon (strained-Si) layer as a method to improve the performance of the CMOS logic inverter by using technology computer aided design simulation. The lattice constant mismatch between the core region and the shell region causes the global strain of the Si region of the shell, which in turn changes the Si parameters. This phenomenon effects on the improvement the electrical characteristics in the -type MOSFET (MOSFET). Through this variation, the asymmetry of the electrical characteristics between -type MOSFET (MOSFET) and MOSFET nanowire is considerably compensated. The inverter using the proposed core-shell structure shows the improved CMOS logic inverter characteristics. For example, the core-shell CMOS logic inverter shows performances such as NM = 0.315 V, NM = 0.312 V, of 8.7 ps, and of 21 ps at an operating voltage of V = 0.7 V.
在本文中，我们采用基于硅锗（SiGe）/应变硅（strained-Si）层的垂直核壳纳米线场效应晶体管，通过技术计算机辅助设计模拟来提高CMOS逻辑反相器的性能。核区域与壳区域之间的晶格常数失配会导致壳层Si区域的全局应变，进而改变Si参数。这种现象影响了p型金属氧化物半导体场效应晶体管（MOSFET）的电学特性的改善。通过这种变化，p型MOSFET和n型MOSFET纳米线之间电学特性的不对称性得到了显著补偿。采用所提出的核壳结构的反相器展现出了改善的CMOS逻辑反相器特性。例如，核壳CMOS逻辑反相器在工作电压Vdd = 0.7 V时，表现出如NMp = 0.315 V、NM n = 0.312 V、传播延迟tpd为8.7 ps以及上升时间tr为21 ps等性能。
