Institute of Computer Systems, Odessa National Polytechnic University, 65044 Odessa, Ukraine.
Faculty of Electrical and Computer Engineering, Cracow University of Technology, 31-155 Cracow, Poland.
Sensors (Basel). 2021 Jan 25;21(3):792. doi: 10.3390/s21030792.
This paper presents a power-oriented monitoring of clock signals that is designed to avoid synchronization failure in computer systems such as FPGAs. The proposed design reduces power consumption and increases the power-oriented checkability in FPGA systems. These advantages are due to improvements in the evaluation and measurement of corresponding energy parameters. Energy parameter orientation has proved to be a good solution for detecting a synchronization failure that blocks logic monitoring circuits. Key advantages lay in the possibility to detect a synchronization failure hidden in safety-related systems by using traditional online testing that is based on logical checkability. Two main types of power-oriented monitoring are considered: detecting a synchronization failure based on the consumption and the dissipation of power, which uses temperature and current consumption sensors, respectively. The experiments are performed on real FPGA systems with the controlled synchronization disconnection and the use of the computer-aided design (CAD) utility to estimate the decreasing values of the energy parameters. The results demonstrate the limited checkability of FPGA systems when using the thermal monitoring of clock signals and success in monitoring by the consumption current.
本文提出了一种面向功率的时钟信号监控方法，旨在避免 FPGA 等计算机系统中的同步故障。该设计降低了功耗，并提高了 FPGA 系统中面向功率的可检查性。这些优势归因于对相应能量参数的评估和测量的改进。能量参数定向已被证明是检测阻塞逻辑监控电路的同步故障的有效解决方案。主要优点在于，通过使用基于逻辑可检查性的传统在线测试，可以检测到隐藏在与安全相关系统中的同步故障。考虑了两种主要类型的面向功率的监控：基于功耗和功率耗散的同步故障检测，分别使用温度和电流消耗传感器。在具有受控同步断开的实际 FPGA 系统上进行实验，并使用计算机辅助设计 (CAD) 工具来估计能量参数的减小值。结果表明，在使用时钟信号的热监控时，FPGA 系统的可检查性有限，而通过电流消耗进行监控则取得了成功。
